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([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id c1-20020a170902848100b001b801044466sm7400745plo.114.2023.07.14.02.59.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Jul 2023 02:59:42 -0700 (PDT) Sender: Guenter Roeck Message-ID: <0ba3767c-d481-6e2c-2d32-b79af0e1efd8@roeck-us.net> Date: Fri, 14 Jul 2023 02:59:40 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [v6 2/4] dt-bindings: hwmon: Add ASPEED TACH Control documentation Content-Language: en-US To: Krzysztof Kozlowski , =?UTF-8?B?6JSh5om/6YGU?= , "jdelvare@suse.com" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "joel@jms.id.au" , "andrew@aj.id.au" , "thierry.reding@gmail.com" , "u.kleine-koenig@pengutronix.de" , "corbet@lwn.net" , "p.zabel@pengutronix.de" , "linux-hwmon@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "linux-pwm@vger.kernel.org" , "linux-doc@vger.kernel.org" , "patrick@stwcx.xyz" , Billy Tsai References: <0b9dd5cf-f4ca-2e6b-624d-0b451bbc2f30@linaro.org> From: Guenter Roeck In-Reply-To: <0b9dd5cf-f4ca-2e6b-624d-0b451bbc2f30@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/14/23 00:13, Krzysztof Kozlowski wrote: > On 14/07/2023 09:04, 蔡承達 wrote: > >> > This is because our register layout for PWM and Tach is not >> continuous. >> >> > PWM0 used 0x0 0x4, Tach0 used 0x8 0xc >> >> > PWM1 used 0x10 0x14, Tach1 used 0x18 0x1c >> >> > ... >> >> > Each PWM/Tach instance has its own controller register and is not >> dependent on others. > > Your email reply quoting style is very difficult to read. > >> >> >> >> Hi Guenter, >> >> >> >> Did you receive a response to my previous email? >> >> I would like to inquire if you have any further concerns regarding the PWM >> and Tach with 16 instances. > > But isn't like this in all PWMs in all SoCs? > Correct, pretty much every fan controller is implemented that way. I don't understand the logic. Guenter