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bh=G5S/Su+LnonQlJtv6h9aSSkyuGTPnasq4Gs6B9RnTFM=; b=DIWftiVk3G0Jw465u9czy8fko4b0Bth8DLlUgnZemU6S9QOZ36tW4DM7NegeXKMReX fmSoIyuIRaSwke+Mn6bHVA22F6SN40IftAk1qEYhBa+ckkR2BUGK9MLfDC6FLAmsUvdL T78ZZ0UeNxOKZmDiA9vSM/wYNGPHc0PmfMaN9GIk/UcEEr7dSU8gdZZHNqpbLyPvAMjt FoDekVafzAnv5uyuciJS8iOg9LoG9MhIcDYe0dOpwnWFOP+X/2mxFY+bLKsHhmfF4nVE y2wfJNQamZgeLmJxztZt4QJXl3PU7SyOlGqYOjaJk7k+NLY+DtOmCI268LB+vEXYitml MVWw== X-Gm-Message-State: ABy/qLYxlTLZp06wpA8xeLY2dfct76VDVXCuvNzXIHi52XrdtiGoBqjq MHK66tqdB3YQdIrcvcKdHxffFkQVDTpo+4EeBcA= X-Received: by 2002:a05:6808:13cf:b0:3a3:820e:2f05 with SMTP id d15-20020a05680813cf00b003a3820e2f05mr4930470oiw.1.1689329919411; Fri, 14 Jul 2023 03:18:39 -0700 (PDT) MIME-Version: 1.0 References: <0b9dd5cf-f4ca-2e6b-624d-0b451bbc2f30@linaro.org> <0ba3767c-d481-6e2c-2d32-b79af0e1efd8@roeck-us.net> In-Reply-To: <0ba3767c-d481-6e2c-2d32-b79af0e1efd8@roeck-us.net> From: =?UTF-8?B?6JSh5om/6YGU?= Date: Fri, 14 Jul 2023 18:18:28 +0800 Message-ID: Subject: Re: [v6 2/4] dt-bindings: hwmon: Add ASPEED TACH Control documentation To: Guenter Roeck Cc: Krzysztof Kozlowski , "jdelvare@suse.com" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "joel@jms.id.au" , "andrew@aj.id.au" , "thierry.reding@gmail.com" , "u.kleine-koenig@pengutronix.de" , "corbet@lwn.net" , "p.zabel@pengutronix.de" , "linux-hwmon@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "linux-pwm@vger.kernel.org" , "linux-doc@vger.kernel.org" , "patrick@stwcx.xyz" , Billy Tsai Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Guenter Roeck =E6=96=BC 2023=E5=B9=B47=E6=9C=8814=E6= =97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=885:59=E5=AF=AB=E9=81=93=EF=BC=9A > > On 7/14/23 00:13, Krzysztof Kozlowski wrote: > > On 14/07/2023 09:04, =E8=94=A1=E6=89=BF=E9=81=94 wrote: > > > >> > This is because our register layout for PWM and Tach is not > >> continuous. > >> > >> > PWM0 used 0x0 0x4, Tach0 used 0x8 0xc > >> > >> > PWM1 used 0x10 0x14, Tach1 used 0x18 0x1c > >> > >> > ... > >> > >> > Each PWM/Tach instance has its own controller register and = is not > >> dependent on others. > > > > Your email reply quoting style is very difficult to read. > > > >> > >> > >> > >> Hi Guenter, > >> > >> > >> > >> Did you receive a response to my previous email? > >> > >> I would like to inquire if you have any further concerns regarding the= PWM > >> and Tach with 16 instances. > > > > But isn't like this in all PWMs in all SoCs? > > > > Correct, pretty much every fan controller is implemented that way. > I don't understand the logic. > Hi Krzysztof and Guenter, Apologies for any confusion earlier. So, you think that the implementation with 16 instances of TACH/PWM device nodes in dts instead of one is ok to you, right? Thanks Best regards, Billy Tsai