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Date:   Fri, 14 Jul 2023 12:52:04 +0100
From:   Mark Brown <broonie@kernel.org>
To:     William Qiu <william.qiu@starfivetech.com>
Cc:     Rob Herring <robh@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        devicetree@vger.kernel.org, linux-spi@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        Linus Walleij <linus.walleij@linaro.org>
Subject: Re: [PATCH v2 2/3] dt-bindings: spi: constrain minItems of clocks
 and clock-names
Message-ID: <9891a7e3-0fce-4d05-8ead-3c0ed155d725@sirena.org.uk>
References: <20230713090015.127541-1-william.qiu@starfivetech.com>
 <20230713090015.127541-3-william.qiu@starfivetech.com>
 <c5ad1e1c-58f4-4833-b9c7-8876c1a0dc27@sirena.org.uk>
 <e3fd0d3f-3fe4-2e23-2548-ecbd487e9c9f@linaro.org>
 <20230713145724.GA3975811-robh@kernel.org>
 <df9de3d8-09da-2b80-b2b4-626cd92fe971@starfivetech.com>
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        protocol="application/pgp-signature"; boundary="klm57L7u8qYMNEjf"
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On Fri, Jul 14, 2023 at 03:14:59PM +0800, William Qiu wrote:
> On 2023/7/13 22:57, Rob Herring wrote:

> > I suspect that PCLK and SSPCLK are tied to the same clock source. There=
=20
> > must be an SSPCLK because that is the one used to clock the SPI bus and=
=20
> > we need to know the frequency of it.

> After communicating with colleagues in SoC FE, I learned that PCLK and
> SSPCLK were homologous on JH7110. He said that SSPCLK would divide the
> frequency internally anyway, and there was no need for external part freq=
uency,
> so he directly gave them together.

> So, should I call this clock ssp_apb or keep it SSPCLK?

I'd expect this to be handled in the DTS for the SoC - connect both
clocks the binding requires to whatever the upstream clock is, it's not
clear to me that any binding change is required.

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Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmSxNuQACgkQJNaLcl1U
h9BFZgf9HdG+QzvFSo2OFGvw81HEFNCptH1B6hNOBEplLpmTioP2hTn7SE22nAoP
M8yy78/dMrerUMSs8l8nTWX2MvtyEhMPWrYi3vUyQhzDz1vPAj2ao4V/5zBD2P/s
xQ00phl+51kJqZ+YX5WXydz9G5EP+usoFq2i2R9ZNPgCm9Y9txRr3+CVOXQOBixW
dOFZYO+/6jfEoEOZyL1Ine5ggi4tD5Q9Q8zLMhS47XKv3me71twVFVxatUate6Cu
gg8tpmFVCiR63fSnrgbRunZjF7R2Ogfg3M7Pg5AUSiJjbMMPAnTKcZrIRM9q11sg
hZ+IpYQkDLUbk5g9cJlhw+cy1Y2egw==
=1P4J
-----END PGP SIGNATURE-----

--klm57L7u8qYMNEjf--