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Message-ID: <b8b2db1b-dbfc-591e-f074-1366e5ac576a@linaro.org>
Date:   Sat, 15 Jul 2023 16:10:09 +0200
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Subject: Re: [PATCH 1/2] clk: qcom: ipq5332: drop the mem noc clocks
Content-Language: en-US
To:     Kathiravan T <quic_kathirav@quicinc.com>,
        Bjorn Andersson <andersson@kernel.org>,
        Andy Gross <agross@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>, linux-arm-msm@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Cc:     quic_srichara@quicinc.com, quic_sjaganat@quicinc.com,
        quic_anusha@quicinc.com, quic_saahtoma@quicinc.com
References: <20230710102807.1189942-1-quic_kathirav@quicinc.com>
 <20230710102807.1189942-2-quic_kathirav@quicinc.com>
From:   Konrad Dybcio <konrad.dybcio@linaro.org>
In-Reply-To: <20230710102807.1189942-2-quic_kathirav@quicinc.com>
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Precedence: bulk

On 10.07.2023 12:28, Kathiravan T wrote:
> Due to the recent design changes, all the mem noc clocks will be
> configured by the bootloaders and it will be access protected by the TZ
> firmware. So drop these clocks from the GCC driver.
> 
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
Are there any IPQ5332s outside Qualcomm labs that will presumably
never get that TZ update?

Konrad
>  drivers/clk/qcom/gcc-ipq5332.c | 95 ----------------------------------
>  1 file changed, 95 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
> index a75ab88ed14c..939925baa9eb 100644
> --- a/drivers/clk/qcom/gcc-ipq5332.c
> +++ b/drivers/clk/qcom/gcc-ipq5332.c
> @@ -1635,42 +1635,6 @@ static struct clk_branch gcc_mdio_slave_ahb_clk = {
>  	},
>  };
>  
> -static struct clk_branch gcc_mem_noc_q6_axi_clk = {
> -	.halt_reg = 0x19010,
> -	.halt_check = BRANCH_HALT,
> -	.clkr = {
> -		.enable_reg = 0x19010,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(const struct clk_init_data) {
> -			.name = "gcc_mem_noc_q6_axi_clk",
> -			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_q6_axim_clk_src.clkr.hw,
> -			},
> -			.num_parents = 1,
> -			.flags = CLK_SET_RATE_PARENT,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
> -static struct clk_branch gcc_mem_noc_ts_clk = {
> -	.halt_reg = 0x19028,
> -	.halt_check = BRANCH_HALT_VOTED,
> -	.clkr = {
> -		.enable_reg = 0x19028,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(const struct clk_init_data) {
> -			.name = "gcc_mem_noc_ts_clk",
> -			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_qdss_tsctr_div8_clk_src.hw,
> -			},
> -			.num_parents = 1,
> -			.flags = CLK_SET_RATE_PARENT,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>  static struct clk_branch gcc_nss_ts_clk = {
>  	.halt_reg = 0x17018,
>  	.halt_check = BRANCH_HALT_VOTED,
> @@ -3339,42 +3303,6 @@ static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
>  	},
>  };
>  
> -static struct clk_branch gcc_mem_noc_ahb_clk = {
> -	.halt_reg = 0x1900c,
> -	.halt_check = BRANCH_HALT,
> -	.clkr = {
> -		.enable_reg = 0x1900c,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(const struct clk_init_data) {
> -			.name = "gcc_mem_noc_ahb_clk",
> -			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> -			},
> -			.num_parents = 1,
> -			.flags = CLK_SET_RATE_PARENT,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
> -static struct clk_branch gcc_mem_noc_apss_axi_clk = {
> -	.halt_reg = 0x1901c,
> -	.halt_check = BRANCH_HALT_VOTED,
> -	.clkr = {
> -		.enable_reg = 0xb004,
> -		.enable_mask = BIT(6),
> -		.hw.init = &(const struct clk_init_data) {
> -			.name = "gcc_mem_noc_apss_axi_clk",
> -			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_apss_axi_clk_src.clkr.hw,
> -			},
> -			.num_parents = 1,
> -			.flags = CLK_SET_RATE_PARENT,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>  static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
>  	.reg = 0x2e010,
>  	.shift = 0,
> @@ -3390,24 +3318,6 @@ static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
>  	},
>  };
>  
> -static struct clk_branch gcc_mem_noc_qosgen_extref_clk = {
> -	.halt_reg = 0x19024,
> -	.halt_check = BRANCH_HALT,
> -	.clkr = {
> -		.enable_reg = 0x19024,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(const struct clk_init_data) {
> -			.name = "gcc_mem_noc_qosgen_extref_clk",
> -			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_snoc_qosgen_extref_div_clk_src.clkr.hw,
> -			},
> -			.num_parents = 1,
> -			.flags = CLK_SET_RATE_PARENT,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>  static struct clk_regmap *gcc_ipq5332_clocks[] = {
>  	[GPLL0_MAIN] = &gpll0_main.clkr,
>  	[GPLL0] = &gpll0.clkr,
> @@ -3451,8 +3361,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
>  	[GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
>  	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
>  	[GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr,
> -	[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
> -	[GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,
>  	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
>  	[GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
>  	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
> @@ -3573,10 +3481,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
>  	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
>  	[GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr,
>  	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
> -	[GCC_MEM_NOC_AHB_CLK] = &gcc_mem_noc_ahb_clk.clkr,
> -	[GCC_MEM_NOC_APSS_AXI_CLK] = &gcc_mem_noc_apss_axi_clk.clkr,
>  	[GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr,
> -	[GCC_MEM_NOC_QOSGEN_EXTREF_CLK] = &gcc_mem_noc_qosgen_extref_clk.clkr,
>  	[GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr,
>  	[GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
>  	[GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,