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From:   David Spickett <David.Spickett@arm.com>
To:     Mark Brown <broonie@kernel.org>,
        Catalin Marinas <Catalin.Marinas@arm.com>,
        Will Deacon <will@kernel.org>, Shuah Khan <shuah@kernel.org>
CC:     "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-kselftest@vger.kernel.org" <linux-kselftest@vger.kernel.org>,
        "stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH 1/3] arm64/fpsimd: Ensure SME storage is allocated after
 SVE VL changes
Thread-Topic: [PATCH 1/3] arm64/fpsimd: Ensure SME storage is allocated after
 SVE VL changes
Thread-Index: AQHZtcYpaNEcPWFzOk2rqQzUt4IivK+91Ua0
Date:   Mon, 17 Jul 2023 11:19:15 +0000
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References: <20230713-arm64-fix-sve-sme-vl-change-v1-0-129dd8611413@kernel.org>
 <20230713-arm64-fix-sve-sme-vl-change-v1-1-129dd8611413@kernel.org>
In-Reply-To: <20230713-arm64-fix-sve-sme-vl-change-v1-1-129dd8611413@kernel.org>
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I've confirmed on QEMU and Arm's FVP that this fixes the issue I was seeing=
.=0A=
=0A=
=0A=
From: Mark Brown <broonie@kernel.org>=0A=
Sent: 13 July 2023 21:06=0A=
To: Catalin Marinas <Catalin.Marinas@arm.com>; Will Deacon <will@kernel.org=
>; Shuah Khan <shuah@kernel.org>=0A=
Cc: David Spickett <David.Spickett@arm.com>; linux-arm-kernel@lists.infrade=
ad.org <linux-arm-kernel@lists.infradead.org>; linux-kernel@vger.kernel.org=
 <linux-kernel@vger.kernel.org>; linux-kselftest@vger.kernel.org <linux-kse=
lftest@vger.kernel.org>; Mark Brown <broonie@kernel.org>; stable@vger.kerne=
l.org <stable@vger.kernel.org>=0A=
Subject: [PATCH 1/3] arm64/fpsimd: Ensure SME storage is allocated after SV=
E VL changes =0A=
=A0=0A=
When we reconfigure the SVE vector length we discard the backing storage=0A=
for the SVE vectors and then reallocate on next SVE use, leaving the SME=0A=
specific state alone. This means that we do not enable SME traps if they=0A=
were already disabled. That means that userspace code can enter streaming=
=0A=
mode without trapping, putting the task in a state where if we try to save=
=0A=
the state of the task we will fault.=0A=
=0A=
Since the ABI does not specify that changing the SVE vector length disturbs=
=0A=
SME state, and since SVE code may not be aware of SME code in the process,=
=0A=
we shouldn't simply discard any ZA state. Instead immediately reallocate=0A=
the storage for SVE if SME is active, and disable SME if we change the SVE=
=0A=
vector length while there is no SME state active.=0A=
=0A=
Disabling SME traps on SVE vector length changes would make the overall=0A=
code more complex since we would have a state where we have valid SME state=
=0A=
stored but might get a SME trap.=0A=
=0A=
Fixes: 9e4ab6c89109 ("arm64/sme: Implement vector length configuration prct=
l()s")=0A=
Reported-by: David Spickett <David.Spickett@arm.com>=0A=
Signed-off-by: Mark Brown <broonie@kernel.org>=0A=
Cc: stable@vger.kernel.org=0A=
---=0A=
=A0arch/arm64/kernel/fpsimd.c | 32 +++++++++++++++++++++++++-------=0A=
=A01 file changed, 25 insertions(+), 7 deletions(-)=0A=
=0A=
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c=0A=
index 7a1aeb95d7c3..a527b95c06e7 100644=0A=
--- a/arch/arm64/kernel/fpsimd.c=0A=
+++ b/arch/arm64/kernel/fpsimd.c=0A=
@@ -847,6 +847,9 @@ void sve_sync_from_fpsimd_zeropad(struct task_struct *t=
ask)=0A=
=A0int vec_set_vector_length(struct task_struct *task, enum vec_type type,=
=0A=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0 unsigned long vl, unsigned long flags)=0A=
=A0{=0A=
+=A0=A0=A0=A0=A0=A0 bool free_sme =3D false;=0A=
+=A0=A0=A0=A0=A0=A0 bool alloc_sve =3D true;=0A=
+=0A=
=A0=A0=A0=A0=A0=A0=A0=A0 if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT |=
=0A=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 PR_SVE_SET_VL_ONEXEC))=0A=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return -EINVAL;=0A=
@@ -897,22 +900,37 @@ int vec_set_vector_length(struct task_struct *task, e=
num vec_type type,=0A=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 task->thread.fp_type =3D F=
P_STATE_FPSIMD;=0A=
=A0=A0=A0=A0=A0=A0=A0=A0 }=0A=
=A0=0A=
-=A0=A0=A0=A0=A0=A0 if (system_supports_sme() && type =3D=3D ARM64_VEC_SME)=
 {=0A=
-=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 task->thread.svcr &=3D ~(SVCR_S=
M_MASK |=0A=
-=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 SVCR_ZA_MASK);=0A=
-=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 clear_thread_flag(TIF_SME);=0A=
+=A0=A0=A0=A0=A0=A0 if (system_supports_sme()) {=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 if (type =3D=3D ARM64_VEC_SME |=
|=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 !(task->thread.svcr=
 & (SVCR_SM_MASK | SVCR_ZA_MASK))) {=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /*=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 * We=
 are changing the SME VL or weren't using=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 * SM=
E anyway, discard the state and force a=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 * re=
allocation.=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 */=
=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 task->t=
hread.svcr &=3D ~(SVCR_SM_MASK |=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 SVCR_ZA_MAS=
K);=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 clear_t=
hread_flag(TIF_SME);=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 free_sm=
e =3D true;=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 } else=A0 {=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 alloc_s=
ve =3D true;=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 }=0A=
=A0=A0=A0=A0=A0=A0=A0=A0 }=0A=
=A0=0A=
=A0=A0=A0=A0=A0=A0=A0=A0 if (task =3D=3D current)=0A=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 put_cpu_fpsimd_context();=
=0A=
=A0=0A=
=A0=A0=A0=A0=A0=A0=A0=A0 /*=0A=
-=A0=A0=A0=A0=A0=A0=A0 * Force reallocation of task SVE and SME state to th=
e correct=0A=
-=A0=A0=A0=A0=A0=A0=A0 * size on next use:=0A=
+=A0=A0=A0=A0=A0=A0=A0 * Free the changed states if they are not in use, th=
ey will=0A=
+=A0=A0=A0=A0=A0=A0=A0 * be reallocated to the correct size on next use.=A0=
 If we need=0A=
+=A0=A0=A0=A0=A0=A0=A0 * SVE state due to having untouched SME state then r=
eallocate=0A=
+=A0=A0=A0=A0=A0=A0=A0 * it immediately.=0A=
=A0=A0=A0=A0=A0=A0=A0=A0=A0 */=0A=
=A0=A0=A0=A0=A0=A0=A0=A0 sve_free(task);=0A=
-=A0=A0=A0=A0=A0=A0 if (system_supports_sme() && type =3D=3D ARM64_VEC_SME)=
=0A=
+=A0=A0=A0=A0=A0=A0 if (free_sme)=0A=
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 sme_free(task);=0A=
+=A0=A0=A0=A0=A0=A0 if (alloc_sve)=0A=
+=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 sve_alloc(task, true);=0A=
=A0=0A=
=A0=A0=A0=A0=A0=A0=A0=A0 task_set_vl(task, type, vl);=0A=
=A0=0A=
=0A=
-- =0A=
2.30.2=0A=