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From:   Chih-Jen Hung <kobedylan@gmail.com>
Date:   Tue, 18 Jul 2023 10:07:10 +0800
Message-ID: <CAKohO56am94Rf5YyEFXaye6=R+Z7bdrQT5G1KaLH+0xrUU=tfQ@mail.gmail.com>
Subject: Re: [PATCH v2] dt-bindings: clock: ast2600: Add I3C and MAC reset definitions
To:     Conor Dooley <conor@kernel.org>
Cc:     "mturquette@baylibre.com" <mturquette@baylibre.com>,
        "sboyd@kernel.org" <sboyd@kernel.org>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "krzysztof.kozlowski+dt@linaro.org" 
        <krzysztof.kozlowski+dt@linaro.org>,
        "conor+dt@kernel.org" <conor+dt@kernel.org>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        BMC-SW <BMC-SW@aspeedtech.com>,
        Chih-Jen Hung <kobedylan@gmail.com>
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Chih-Jen Hung <kobedylan@gmail.com> =E6=96=BC 2023=E5=B9=B47=E6=9C=8818=E6=
=97=A5 =E9=80=B1=E4=BA=8C =E4=B8=8A=E5=8D=889:59=E5=AF=AB=E9=81=93=EF=BC=9A
>
> On Mon, Jul 17, 2023 at 02:58:58PM +0800, Dylan Hung wrote:
>
> Add reset definitions of AST2600 I3C and MAC controllers.
>
> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
> ---
>   include/dt-bindings/clock/ast2600-clock.h | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
>
> What changed compared to v1?
> Are there any users of the additional resets (eg, in a dts somewhere)?
>
> Thanks,
> Conor.

An existing macro, ASPEED_RESET_I3C_DMA, was removed in V1. However,
considering that this macro may be used somewhere, I have decided to
add it back in V2. I will ensure to include the changelog in V3.

>
>
> diff --git a/include/dt-bindings/clock/ast2600-clock.h
> b/include/dt-bindings/clock/ast2600-clock.h
> index e149eee61588..712782177c90 100644
> --- a/include/dt-bindings/clock/ast2600-clock.h
> +++ b/include/dt-bindings/clock/ast2600-clock.h
> @@ -90,7 +90,19 @@
>   /* Only list resets here that are not part of a clock gate + reset pair=
 */
>   #define ASPEED_RESET_ADC 55
>   #define ASPEED_RESET_JTAG_MASTER2 54
> +
> +#define ASPEED_RESET_MAC4 53
> +#define ASPEED_RESET_MAC3 52
> +
> +#define ASPEED_RESET_I3C5 45
> +#define ASPEED_RESET_I3C4 44
> +#define ASPEED_RESET_I3C3 43
> +#define ASPEED_RESET_I3C2 42
> +#define ASPEED_RESET_I3C1 41
> +#define ASPEED_RESET_I3C0 40
> +#define ASPEED_RESET_I3C 39
>   #define ASPEED_RESET_I3C_DMA 39

This is the macro I added back in V2. There is no reset-line hardware
available for `ASPEED_RESET_I3C_DMA`, so I have added a new macro to
provide a better representation of the hardware design. I will include
the explanation in the commit message of V3.

> +
>   #define ASPEED_RESET_PWM 37
>   #define ASPEED_RESET_PECI 36
>   #define ASPEED_RESET_MII 35
> --
> 2.25.1