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Message-ID: <4e4dea7f-639b-71aa-5a47-95ce14d7f1ed@starfivetech.com>
Date:   Tue, 18 Jul 2023 13:48:09 +0800
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Subject: Re: [PATCH v7 0/7] Add PLL clocks driver and syscon for StarFive
 JH7110 SoC
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To:     Conor Dooley <conor@kernel.org>
CC:     <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
        "Michael Turquette" <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        "Rob Herring" <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Hal Feng <hal.feng@starfivetech.com>,
        William Qiu <william.qiu@starfivetech.com>,
        <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
References: <20230717023040.78860-1-xingyu.wu@starfivetech.com>
 <20230717-easel-pessimist-5b7c4e5bed0a@spud>
From:   Xingyu Wu <xingyu.wu@starfivetech.com>
In-Reply-To: <20230717-easel-pessimist-5b7c4e5bed0a@spud>
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On 2023/7/18 2:14, Conor Dooley wrote:
> Hey Xingyu,
> 
> On Mon, Jul 17, 2023 at 10:30:33AM +0800, Xingyu Wu wrote:
>> This patch serises are to add PLL clocks driver and providers by writing
>> and reading syscon registers for the StarFive JH7110 RISC-V SoC. And add 
>> documentation and nodes to describe StarFive System Controller(syscon)
>> Registers. This patch serises are based on Linux 6.4.
>> 
>> PLLs are high speed, low jitter frequency synthesizers in JH7110.
>> Each PLL clock works in integer mode or fraction mode by some dividers,
>> and the dividers are set in several syscon registers.
>> The formula for calculating frequency is: 
>> Fvco = Fref * (NI + NF) / M / Q1
>> 
>> The first patch adds docunmentation to describe PLL clock bindings,
>> and the second patch adds documentation to decribe syscon registers.
>> The patch 3 modifies the SYSCRG bindings and adds PLL clock inputs.
>> The patch 4 adds driver to support PLL clocks for JH7110.
>> The patch 5 modifies the system clock driver and can select the PLL clock
>> source from PLL clocks driver. And the patch 6 adds the 
>> stg/sys/aon syscon nodes for JH7110 SoC. The last patch modifies the 
>> syscrg node in JH7110 dts file.
> 
> Just FYI, I have picked up the binding & clock portions of this series
> and your other one adding the stg syscon. I've pushed them out here for
> the test robots to have a look:
> https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=clk-starfive
> 
> If that passes, my plan is to send Stephen a PR for the lot, later this
> week.
> 

Great. Thank you for everything.

Best regards,
Xingyu Wu