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Message-ID: <78b06bf0-ab71-acdf-5799-1f6d849e7ead@linaro.org>
Date:   Tue, 18 Jul 2023 08:11:12 +0200
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Subject: Re: [PATCH] usb: dwc2: add new compatible for Intel SoCFPGA Stratix10
 platform
Content-Language: en-US
To:     Meng Li <Meng.Li@windriver.com>, dinguyen@kernel.org,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, devicetree@vger.kernel.org
Cc:     linux-kernel@vger.kernel.org
References: <20230718030851.2014306-1-Meng.Li@windriver.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <20230718030851.2014306-1-Meng.Li@windriver.com>
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On 18/07/2023 05:08, Meng Li wrote:
> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
> the Stratix platform also does not support clock-gating. The commit
> 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's Agilex")
> had fixed this issue. So, add the essential compatible to also use the
> specific data on Stratix10 platform.
> 
> Signed-off-by: Meng Li <Meng.Li@windriver.com>
> ---
>  arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index ea788a920eab..b8dd5509c214 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -490,7 +490,7 @@ usbphy0: usbphy@0 {
>  		};
>  
>  		usb0: usb@ffb00000 {
> -			compatible = "snps,dwc2";
> +			compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";

You miss SoC specific compatible.

Best regards,
Krzysztof