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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id p1-20020adff201000000b003141f3843e6sm1677348wro.90.2023.07.18.01.37.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Jul 2023 01:37:17 -0700 (PDT) Message-ID: <59a88e00-0758-32b8-7ce4-8dea84a9b0f7@baylibre.com> Date: Tue, 18 Jul 2023 10:37:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 2/2] clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes To: AngeloGioacchino Del Regno , Maxime Ripard Cc: Chen-Yu Tsai , sboyd@kernel.org, mturquette@baylibre.com, matthias.bgg@gmail.com, msp@baylibre.com, yangyingliang@huawei.com, u.kleine-koenig@pengutronix.de, miles.chen@mediatek.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com References: <20230713072138.84117-1-angelogioacchino.delregno@collabora.com> <20230713072138.84117-3-angelogioacchino.delregno@collabora.com> <9a0817c2-4101-5c21-977d-77ac0d83a067@baylibre.com> <25724ee3-858a-01eb-352b-3edbfad31c8e@collabora.com> <24d17b07-1e8d-05f6-46b7-9da1ff1bed7a@collabora.com> Content-Language: en-US From: Alexandre Mergnat In-Reply-To: <24d17b07-1e8d-05f6-46b7-9da1ff1bed7a@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/07/2023 16:30, AngeloGioacchino Del Regno wrote: >>>>> However I'm not sure if that works for parents. It should, given the >>>>> original use case was for the sunxi platforms, which like the MediaTek >>>>> platform here has 2 PLLs for video related consumers, but I couldn't >>>>> find code verifying it. >>>> >>>> If you want to prevent clocks from ever being reparented, you can use >>>> the new clk_hw_determine_rate_no_reparent() determine_rate >>>> implementation. >>>> >>> >>> We want the clocks to be reparented, as we need them to switch >>> parents as >>> explained before... that's more or less how the tree looks: >>> >>> TVDPLL(x) -> PLL Divider (fixed) -> MUX -> Gate -> Controller >>> >>> Besides, I think that forcing *one* parent to the dp/edp mux would >>> produce a >>> loss of the flexibility that the clock framework provides. >>> >>> I again want to emphasize on the fact that TVDPLL1 and TVDPLL2 are >>> *identical* >>> in specs, and on that there will never be a MT8195 SoC that has only >>> one of >>> the two PLLs, for obvious reasons... >>> >>> P.S.: If you need more context, I'll be glad to answer to any other >>> question! >> >> Then I have no idea what the question is :) >> >> What are you trying to achieve / fix, and how can I help you ? :) >> > > Chen-Yu, Alexandre had/have questions about if there was any other > solution instead > of using the solution of *this* commit, so, if there's any other better > solution > than the one that I've sent as this commit. > > I'm the one saying that this commit is the best solution :-P Hi Angelo, My solution is based on PLL static allocation, because I missed it could be reparented actually. I think I've a better understanding of this commit now, thanks to your explanations. Looks fine for me. Reviewed-by: Alexandre Mergnat -- Regards, Alexandre