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Date:   Tue, 18 Jul 2023 11:41:38 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Jisheng Zhang <jszhang@kernel.org>
Cc:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for
 !dma_coherent
Message-ID: <20230718-regulator-hardened-919cb8f4e562@spud>
References: <20230716165147.1897-1-jszhang@kernel.org>
 <20230716165147.1897-3-jszhang@kernel.org>
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On Mon, Jul 17, 2023 at 12:51:47AM +0800, Jisheng Zhang wrote:
> With the DMA bouncing of unaligned kmalloc() buffers now in place,
> enable it for riscv when RISCV_DMA_NONCOHERENT=3Dy to allow the
> kmalloc-{8,16,32,96} caches. Since RV32 doesn't enable SWIOTLB
> yet, and I didn't see any dma noncoherent RV32 platforms in the
> mainline, so skip RV32 now by only enabling
> DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB is available. Once we see
> such requirement on RV32, we can enable it then.
>=20
> NOTE: we didn't force to create the swiotlb buffer even when the
> end of RAM is within the 32-bit physical address range. That's to
> say:
> For RV64 with > 4GB memory, the feature is enabled.
> For RV64 with <=3D 4GB memory, the feature isn't enabled by default. We
> rely on users to pass "swiotlb=3Dmmnn,force" where mmnn is the Number of
> I/O TLB slabs, see kernel-parameters.txt for details.
>=20
> Tested on Sipeed Lichee Pi 4A with 8GB DDR and Sipeed M1S BL808 Dock
> board.
>=20
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

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