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From:   William-tw Lin <william-tw.lin@mediatek.com>
To:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>,
        Kevin Hilman <khilman@kernel.org>
CC:     <Project_Global_Chrome_Upstream_Group@mediatek.com>,
        <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>,
        <linux-mediatek@lists.infradead.org>,
        William-tw Lin <william-tw.lin@mediatek.com>
Subject: [PATCH 3/3] arm64: dts: Add node for chip info driver
Date:   Tue, 18 Jul 2023 19:21:43 +0800
Message-ID: <20230718112143.14036-4-william-tw.lin@mediatek.com>
In-Reply-To: <20230718112143.14036-1-william-tw.lin@mediatek.com>
References: <20230718112143.14036-1-william-tw.lin@mediatek.com>
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Add dts node for socinfo retrieval. This includes the following projects:
MT8173
MT8183
MT8186
MT8192
MT8195

Signed-off-by: William-tw Lin <william-tw.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 15 +++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 15 +++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 10 ++++++++++
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8195.dtsi |  9 +++++++++
 5 files changed, 63 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index c47d7d900f28..115f907751c1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -590,11 +590,26 @@
 			reg = <0 0x10206000 0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
+			socinfo_data1: socinfo-data1 {
+				reg = <0x040 0x4>;
+			};
+
+			socinfo_data2: socinfo-data2 {
+				reg = <0x044 0x4>;
+			};
+
 			thermal_calibration: calib@528 {
 				reg = <0x528 0xc>;
 			};
 		};
 
+		mtk_socinfo: mtk-socinfo {
+			compatible = "mediatek,mt8173-socinfo";
+			nvmem-cells = <&socinfo_data1 &socinfo_data2>;
+			nvmem-cell-names = "socinfo-data1", "socinfo-data2";
+		};
+
 		apmixedsys: clock-controller@10209000 {
 			compatible = "mediatek,mt8173-apmixedsys";
 			reg = <0 0x10209000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5169779d01df..1035c6d7eb91 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1706,6 +1706,15 @@
 			reg = <0 0x11f10000 0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
+			socinfo_data1: socinfo-data1 {
+				reg = <0x04C 0x4>;
+			};
+
+			socinfo_data2: socinfo-data2 {
+				reg = <0x060 0x4>;
+			};
+
 			thermal_calibration: calib@180 {
 				reg = <0x180 0xc>;
 			};
@@ -1719,6 +1728,12 @@
 			};
 		};
 
+		mtk_socinfo: mtk-socinfo {
+			compatible = "mediatek,mt8183-socinfo";
+			nvmem-cells = <&socinfo_data1 &socinfo_data2>;
+			nvmem-cell-names = "socinfo-data1", "socinfo-data2";
+		};
+
 		u3phy: t-phy@11f40000 {
 			compatible = "mediatek,mt8183-tphy",
 				     "mediatek,generic-tphy-v2";
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index f04ae70c470a..e048e4d994e9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1660,6 +1660,16 @@
 				reg = <0x59c 0x4>;
 				bits = <0 3>;
 			};
+
+			socinfo_data1: socinfo-data1 {
+				reg = <0x7a0 0x4>;
+			};
+		};
+
+		mtk_socinfo: socinfo {
+			compatible = "mediatek,mt8186-socinfo";
+			nvmem-cells = <&socinfo_data1>;
+			nvmem-cell-names = "socinfo-data1";
 		};
 
 		mipi_tx0: dsi-phy@11cc0000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 5e94cb4aeb44..80066faf2b2c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1122,6 +1122,14 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			socinfo_data1: socinfo-data1 {
+				reg = <0x044 0x4>;
+			};
+
+			socinfo_data2: socinfo-data2 {
+				reg = <0x050 0x4>;
+			};
+
 			lvts_e_data1: data1@1c0 {
 				reg = <0x1c0 0x58>;
 			};
@@ -1131,6 +1139,12 @@
 			};
 		};
 
+		mtk_socinfo: mtk-socinfo {
+			compatible = "mediatek,mt8192-socinfo";
+			nvmem-cells = <&socinfo_data1 &socinfo_data2>;
+			nvmem-cell-names = "socinfo-data1", "socinfo-data2";
+		};
+
 		i2c3: i2c@11cb0000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11cb0000 0 0x1000>,
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 48b72b3645e1..ec8f2c8888cb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1683,6 +1683,15 @@
 			lvts_efuse_data2: lvts2-calib@1d0 {
 				reg = <0x1d0 0x38>;
 			};
+			socinfo_data1: socinfo-data1 {
+				reg = <0x7a0 0x4>;
+			};
+		};
+
+		mtk_socinfo: socinfo {
+			compatible = "mediatek,mt8195-socinfo";
+			nvmem-cells = <&socinfo_data1>;
+			nvmem-cell-names = "socinfo-data1";
 		};
 
 		u3phy2: t-phy@11c40000 {
-- 
2.18.0