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Message-ID: <d087d0df-0bf6-c93a-7999-f9385ebb7a38@linaro.org>
Date:   Tue, 18 Jul 2023 14:47:55 +0200
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Subject: Re: [PATCH 15/15] arm64: dts: qcom: sm6115: Add VDD_CX to GPU_CCC
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To:     Stephan Gerhold <stephan@gerhold.net>
Cc:     Bjorn Andersson <andersson@kernel.org>,
        Andy Gross <agross@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Marijn Suijten <marijn.suijten@somainline.org>,
        linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org>
 <20230717-topic-branch_aon_cleanup-v1-15-27784d27a4f4@linaro.org>
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From:   Konrad Dybcio <konrad.dybcio@linaro.org>
In-Reply-To: <ZLZ94Qc6x1HyjJPQ@gerhold.net>
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On 18.07.2023 13:56, Stephan Gerhold wrote:
> On Mon, Jul 17, 2023 at 09:18:21PM +0200, Konrad Dybcio wrote:
>> On 17.07.2023 19:23, Stephan Gerhold wrote:
>>> On Mon, Jul 17, 2023 at 07:11:33PM +0200, Konrad Dybcio wrote:
>>>> On 17.07.2023 18:56, Stephan Gerhold wrote:
>>>>> On Mon, Jul 17, 2023 at 06:50:18PM +0200, Konrad Dybcio wrote:
>>>>>> On 17.07.2023 18:28, Stephan Gerhold wrote:
>>>>>>> On Mon, Jul 17, 2023 at 05:19:22PM +0200, Konrad Dybcio wrote:
>>>>>>>> The GPU_CC block is powered by VDD_CX. Describe that.
>>>>>>>>
>>>>>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>>>>>> ---
>>>>>>>>  arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++
>>>>>>>>  1 file changed, 2 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>>>>>>> index 29b5b388cd94..bfaaa1801a4d 100644
>>>>>>>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
>>>>>>>> @@ -1430,6 +1430,8 @@ gpucc: clock-controller@5990000 {
>>>>>>>>  			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
>>>>>>>>  				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
>>>>>>>>  				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
>>>>>>>> +			power-domains = <&rpmpd SM6115_VDDCX>;
>>>>>>>> +			required-opps = <&rpmpd_opp_low_svs>;
>>>>>>>
>>>>>>> Where is this required-opp coming from? The clocks in gpucc seem to have
>>>>>>> different voltage requirements depending on the rates, but we usually
>>>>>>> handle that in the OPP tables of the consumer.
>>>>>> The only lower levels defined for this SoC are VDD_MIN and VDD_RET,
>>>>>> but quite obviously the GPU won't work then
>>>>>>
>>>>>
>>>>> The levels needed for the GPU clocks to run should be in the GPU OPP
>>>>> table though, just like e.g. sdhc2_opp_table for the SDCC clocks.
>>>>>
>>>>> I still don't really understand why this is specified here. :)
>>>> The GPU_CC block needs this rail to be at a certain power level for
>>>> register access. This describes that requirement.
>>>>
>>>
>>> Can you show where this is defined downstream? On a quick look I didn't
>>> see something like that anywhere. Or is this from some secret
>>> documentation?
>> As far as downstream goes, you can notice that no branch's or RCG's
>> vdd tables ever define a level lower than the one I mentioned.
>>
> 
> As far as I can tell the vdd tables are only used when the clock is
> actually enabled though, not for writing to registers while they are
> disabled.
Maybe, but you can also notice that even XO rates require at least
SVS_LOW to function.

Konrad