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Date:   Tue, 18 Jul 2023 08:06:11 -0700
From:   Bjorn Andersson <andersson@kernel.org>
To:     Konrad Dybcio <konrad.dybcio@linaro.org>
Cc:     Stephan Gerhold <stephan@gerhold.net>,
        Andy Gross <agross@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Marijn Suijten <marijn.suijten@somainline.org>,
        linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 15/15] arm64: dts: qcom: sm6115: Add VDD_CX to GPU_CCC
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On Tue, Jul 18, 2023 at 02:21:31PM +0200, Konrad Dybcio wrote:
> On 18.07.2023 06:25, Bjorn Andersson wrote:
> > On Mon, Jul 17, 2023 at 07:11:33PM +0200, Konrad Dybcio wrote:
> >> On 17.07.2023 18:56, Stephan Gerhold wrote:
> >>> On Mon, Jul 17, 2023 at 06:50:18PM +0200, Konrad Dybcio wrote:
> >>>> On 17.07.2023 18:28, Stephan Gerhold wrote:
> >>>>> On Mon, Jul 17, 2023 at 05:19:22PM +0200, Konrad Dybcio wrote:
> >>>>>> The GPU_CC block is powered by VDD_CX. Describe that.
> >>>>>>
> >>>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> >>>>>> ---
> >>>>>>  arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++
> >>>>>>  1 file changed, 2 insertions(+)
> >>>>>>
> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> >>>>>> index 29b5b388cd94..bfaaa1801a4d 100644
> >>>>>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> >>>>>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> >>>>>> @@ -1430,6 +1430,8 @@ gpucc: clock-controller@5990000 {
> >>>>>>  			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> >>>>>>  				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> >>>>>>  				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> >>>>>> +			power-domains = <&rpmpd SM6115_VDDCX>;
> >>>>>> +			required-opps = <&rpmpd_opp_low_svs>;
> >>>>>
> >>>>> Where is this required-opp coming from? The clocks in gpucc seem to have
> >>>>> different voltage requirements depending on the rates, but we usually
> >>>>> handle that in the OPP tables of the consumer.
> >>>> The only lower levels defined for this SoC are VDD_MIN and VDD_RET,
> >>>> but quite obviously the GPU won't work then
> >>>>
> >>>
> >>> The levels needed for the GPU clocks to run should be in the GPU OPP
> >>> table though, just like e.g. sdhc2_opp_table for the SDCC clocks.
> >>>
> >>> I still don't really understand why this is specified here. :)
> >> The GPU_CC block needs this rail to be at a certain power level for
> >> register access. This describes that requirement.
> >>
> > 
> > And that is not the lowest level reported by command db?
> > Please describe this part in the commit message as well.
> command-what? ;)
> 

Apparently doesn't matter that I read that line multiple times, my brain
really wanted a 'h' in there.

> RPM exports VDD_NONE (off), VDD_MIN (the lowest state before collapse)
> and then low_svs is usually the lowest "actually on" state for all
> consumers.
> 

In rpmhpd I changed it such that the minimal enabled state would be
!disabled (so that the automatic enablement during probe would be
sufficient to access registers), but talking to Ulf this is
provider-specific.

So unless you can figure out a acceptable lowest non-disabled state this
is what has to be done...


PS. My ask for mentioning this in the commit message still stands.

Regards,
Bjorn