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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l13-20020a17090a660d00b0025eee012ca4si1144084pjj.30.2023.07.19.02.48.36; Wed, 19 Jul 2023 02:48:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230369AbjGSJ0M convert rfc822-to-8bit (ORCPT + 99 others); Wed, 19 Jul 2023 05:26:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231336AbjGSJ0I (ORCPT ); Wed, 19 Jul 2023 05:26:08 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 958221BFC; Wed, 19 Jul 2023 02:25:48 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id A320524E2C2; Wed, 19 Jul 2023 17:25:46 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Jul 2023 17:25:46 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 19 Jul 2023 17:25:45 +0800 From: William Qiu To: , , , CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Ziv Xu , William Qiu Subject: [PATCH v5 0/3] Add initialization of clock for StarFive JH7110 SoC Date: Wed, 19 Jul 2023 17:25:42 +0800 Message-ID: <20230719092545.1961401-1-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, This patchset adds initial rudimentary support for the StarFive Quad SPI controller driver. And this driver will be used in StarFive's VisionFive 2 board. In 6.4, the QSPI_AHB and QSPI_APB clocks changed from the default ON state to the default OFF state, so these clocks need to be enabled in the driver.At the same time, dts patch is added to this series. Changes v4->v5: - Rebased to v6.5rc2. - Changed the way to initialization the clocks. - Changed the layout for the SPI flash. Changes v3->v4: - Added minItems for clocks. - Added clock names property. - Fixed formatting issues. Changes v2->v3: - Rebased to v6.4rc6. - Renamed the clock names. - Changed the variable definition type. Changes v1->v2: - Renamed the clock names. - Specified a different array of clocks. - Used clk_bulk_ APIs. The patch series is based on v6.5rc2. William Qiu (3): dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC .../bindings/spi/cdns,qspi-nor.yaml | 12 +++- .../jh7110-starfive-visionfive-2.dtsi | 36 ++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 19 ++++++ drivers/spi/spi-cadence-quadspi.c | 67 +++++++++++++++++++ 4 files changed, 133 insertions(+), 1 deletion(-) -- 2.34.1