Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Alistair Popple <apopple@nvidia.com>
To:     akpm@linux-foundation.org
Cc:     ajd@linux.ibm.com, catalin.marinas@arm.com, fbarrat@linux.ibm.com,
        iommu@lists.linux.dev, jgg@ziepe.ca, jhubbard@nvidia.com,
        kevin.tian@intel.com, kvm@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-mm@kvack.org, linuxppc-dev@lists.ozlabs.org,
        mpe@ellerman.id.au, nicolinc@nvidia.com, npiggin@gmail.com,
        robin.murphy@arm.com, seanjc@google.com, will@kernel.org,
        x86@kernel.org, zhi.wang.linux@gmail.com,
        Alistair Popple <apopple@nvidia.com>
Subject: [PATCH v2 1/5] arm64/smmu: Use TLBI ASID when invalidating entire range
Date:   Wed, 19 Jul 2023 22:18:42 +1000
Message-Id: <082390057ec33969c81d49d35aa3024d7082b0bd.1689768831.git-series.apopple@nvidia.com>
In-Reply-To: <cover.de78568883814904b78add6317c263bf5bc20234.1689768831.git-series.apopple@nvidia.com>
References: <cover.de78568883814904b78add6317c263bf5bc20234.1689768831.git-series.apopple@nvidia.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?bQkov8O6vBYQf+/MADu+y2q5tsi33513Is6P38978q+2fpzMaqOK68yyxf1j?=
 =?us-ascii?Q?8io1Yd7QHVzDqErhcn3ibomWT5oE5g9wunLAotgyEbh9Ly+ZmPi6rV0nhOOK?=
 =?us-ascii?Q?o3r2S92do6Pw+4hfRCptw9QX+PHMFqwZMxw28/1IfacuQ7Z5e5phBR6dpjru?=
 =?us-ascii?Q?Abi5u3dz08bgM5Nuw82LR0zHu3dZFO9Fy9+d69TiFqKnHPberyeyjOcQrS8Q?=
 =?us-ascii?Q?UzsqOBymnG5DsS+6o7CP7KFypQs/9kSZWh82l+W5w9HA+BuEzMoo1VrzEX2T?=
 =?us-ascii?Q?bhlsbkzio0SnVwkYqOgLNPmaMms79PjYlFQySOQ7aXKH8XIwvJWDSiuVXYG0?=
 =?us-ascii?Q?AJxAoW+fddW6eNLYu2YlmleTSb2L9VOA60a5nHb84hmk5Z0U8IQqUrlzL47g?=
 =?us-ascii?Q?As3uDo9MSQb8dzWiXIOGkJvpMDDPDoP91rHx8RDjlnt0BhXtNlqHuT70m+PF?=
 =?us-ascii?Q?QPq+ASWQ1SaMi6137fWo5swc+qISbGf/yYk4C/QGZYbObUk8Pnd2TGcQWaxp?=
 =?us-ascii?Q?rJpHEGs5hdse5XhoABUayx40zy8m1Ci7c6rEbFwHRIMsARi+hRK78EeVkNtV?=
 =?us-ascii?Q?NqH9ITSBHj+///xX3F/KHPpPg+y6eKsALfCfHr6+0BMsDyNvkO7QNPvzk0vD?=
 =?us-ascii?Q?Ns+8U0GTwuu2on/A52FJ7mcsK64hTjQDtP5Ss96SXaLcdB7hg6d4VNfmiCDK?=
 =?us-ascii?Q?4WV1aXmWAJJzHGsC3R0RAQrwD7SFAqhyhR2Yx/UANDTFEzdYGpVE5jXJqdQV?=
 =?us-ascii?Q?FFsSNzlzYcXQHOBYbXzgULY8m/DF1w16TDGWBuSEmfNYIkORqGFKwpjMPc41?=
 =?us-ascii?Q?e2P1chMDbAmyX0bYvI8zi5NqV0qmpfayp45bZE6SPjrscRHrkVQwLcT1pptp?=
 =?us-ascii?Q?rYqmFyR3eVFBVDMpAnVr2NBeAyDD1BzxV0l7V7VoVkHA1Al4UfMN8muLDOOh?=
 =?us-ascii?Q?eurwlRIbq0hk3IGqSRBNGPHm5p2DrG8qkEGZhFSKRvucyZZZzrCcLGkmMacZ?=
 =?us-ascii?Q?X8V4WeRV8pkypgRu64Gy3dj9S9M+EFCq1ViDKhqQ9F5lvoZVvmUyptyv3lVV?=
 =?us-ascii?Q?IsA6GbGd8As+3O3oNH7TV2VeHfgr5EDhS6xKeXYBbIoCEtPSSfoTj55yYklt?=
 =?us-ascii?Q?VkIPu51piOOjLdOfaOwWsXS1+IQbKdFLU1Sj5s66G90K91YrjAq8MowgD/V0?=
 =?us-ascii?Q?+XChyAmC89UOGtaqE1SLuPEtDJW4u9iZxg8MHQxPTg/DzL6fHf6XHXEnNGpx?=
 =?us-ascii?Q?bl1mWMEJoxQTVL5i0v8iae3Tst7rSSYF4nkWV126U8UliZwsIpsUzZuXgAnw?=
 =?us-ascii?Q?2WULrrSTPKkZb7gilmW8v0NMbJnginGXmD+qfiYFT+OiOtGQJuK07N8pqG9V?=
 =?us-ascii?Q?uHZp7rcqjpyDHYG0jAk1PDY6ddGspVPd3USn8oSdB+pdDF7nTfKufvjYutNN?=
 =?us-ascii?Q?9hxN7EnOXZh/YJMP3rLNcQwSmJNJqM2DJSa5XPQoRsmtYZ7Hjq3dRsEXT0QA?=
 =?us-ascii?Q?PJHUeo9aTcP5/adiLSDqABCPzihSakPIg2B7AP8TOUCRZ7ppFo/8Tm+eGUN+?=
 =?us-ascii?Q?s00VcvWvks/yZtETFxDEopV5O47T/2T9ZDRt5cRr?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: c6dd3030-fd0c-4978-31a7-08db88526064
X-MS-Exchange-CrossTenant-AuthSource: BYAPR12MB3176.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2023 12:19:19.0156
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: McZeyUjgJe1+zjnXcVMVHF1dI6z00ev3axEmdLzDzFWbq7WtqRMAHvf64pqpOx3FxaV3qHNlCKipwFZwuyJkkQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5359
X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,
        DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,
        RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,
        T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no
        version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

The ARM SMMU has a specific command for invalidating the TLB for an
entire ASID. Currently this is used for the IO_PGTABLE API but not for
ATS when called from the MMU notifier.

The current implementation of notifiers does not attempt to invalidate
such a large address range, instead walking each VMA and invalidating
each range individually during mmap removal. However in future SMMU
TLB invalidations are going to be sent as part of the normal
flush_tlb_*() kernel calls. To better deal with that add handling to
use TLBI ASID when invalidating the entire address space.

Signed-off-by: Alistair Popple <apopple@nvidia.com>
---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
index a5a63b1..2a19784 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
@@ -200,10 +200,20 @@ static void arm_smmu_mm_invalidate_range(struct mmu_notifier *mn,
 	 * range. So do a simple translation here by calculating size correctly.
 	 */
 	size = end - start;
+	if (size == ULONG_MAX)
+		size = 0;
+
+	if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM)) {
+		if (!size)
+			arm_smmu_tlb_inv_asid(smmu_domain->smmu,
+					      smmu_mn->cd->asid);
+		else
+			arm_smmu_tlb_inv_range_asid(start, size,
+						    smmu_mn->cd->asid,
+						    PAGE_SIZE, false,
+						    smmu_domain);
+	}
 
-	if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM))
-		arm_smmu_tlb_inv_range_asid(start, size, smmu_mn->cd->asid,
-					    PAGE_SIZE, false, smmu_domain);
 	arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, start, size);
 }
 
-- 
git-series 0.9.1