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References: <20230719-imx8mp_enet_qos_use_125mhz_clock-v1-1-782c9ac6e121@pengutronix.de>
In-Reply-To: <20230719-imx8mp_enet_qos_use_125mhz_clock-v1-1-782c9ac6e121@pengutronix.de>
From:   Fabio Estevam <festevam@gmail.com>
Date:   Wed, 19 Jul 2023 11:03:28 -0300
Message-ID: <CAOMZO5AP1zDQPGnctq+UbPSiv+7Rg=DGABb7-mZV__HZ4qpMBQ@mail.gmail.com>
Subject: Re: [PATCH] arm64: dts: imx8mp: use correct clock for eqos
 timestamping counter
To:     Johannes Zink <j.zink@pengutronix.de>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        NXP Linux Team <linux-imx@nxp.com>,
        patchwork-jzi@pengutronix.de, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
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Hi Johannes,

On Wed, Jul 19, 2023 at 10:59=E2=80=AFAM Johannes Zink <j.zink@pengutronix.=
de> wrote:
>
> The i.MX8MP Reference Manual rev 1 06/2021, section 11.7.2.5 "Timestamp
> Support" indicates the PTP timestamp clock expects a typical frequency
> of 125MHz.
>
> As this also improves the precision of the measured timestamps: assign
> appropriate 125MHz Clock parent. As no one except the timestamping
> counter uses this clock, there are no side-effects of this change in
> other peripherals.
>
> Signed-off-by: Johannes Zink <j.zink@pengutronix.de>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/=
dts/freescale/imx8mp.dtsi
> index 6f2f50e1639c..7f80dff914c2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1334,7 +1334,7 @@ eqos: ethernet@30bf0000 {
>                                                   <&clk IMX8MP_CLK_ENET_Q=
OS_TIMER>,
>                                                   <&clk IMX8MP_CLK_ENET_Q=
OS>;
>                                 assigned-clock-parents =3D <&clk IMX8MP_S=
YS_PLL1_266M>,
> -                                                        <&clk IMX8MP_SYS=
_PLL2_100M>,
> +                                                        <&clk IMX8MP_SYS=
_PLL2_125M>,
>                                                          <&clk IMX8MP_SYS=
_PLL2_125M>;
>                                 assigned-clock-rates =3D <0>, <100000000>=
, <125000000>;

Shouldn't this also be changed to:

assigned-clock-rates =3D <0>, <125000000>, <125000000>;