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From:   Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
To:     <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-cxl@vger.kernel.org>
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        Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@linux.intel.com>,
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        Yazen Ghannam <yazen.ghannam@amd.com>,
        Terry Bowman <terry.bowman@amd.com>,
        Robert Richter <rrichter@amd.com>,
        Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Subject: [PATCH 0/2] PCI, AER, CXL: Fix appropriate _OSC check for CXL RAS Cap
Date:   Wed, 19 Jul 2023 19:23:11 +0000
Message-ID: <20230719192313.38591-1-Smita.KoralahalliChannabasappa@amd.com>
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This series of patches fixes the appropriate _OSC check for CXL RAS
registers.

First patch moves around pcie_aer_is_native() function declaration to a
common location to be used by cxl/pci module.

Second patch addresses the _OSC check.

Smita Koralahalli (2):
  PCI, AER: Export and make pcie_aer_is_native() global
  cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS
    registers

 drivers/cxl/pci.c          | 7 +++----
 drivers/pci/pcie/aer.c     | 1 +
 drivers/pci/pcie/portdrv.h | 2 --
 include/linux/aer.h        | 2 ++
 4 files changed, 6 insertions(+), 6 deletions(-)

-- 
2.17.1