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Subject: Re: [PATCH v5 3/3] clk: imx: imx8: add audio clock mux driver
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
To:     Shengjiu Wang <shengjiu.wang@nxp.com>, abelvesa@kernel.org,
        conor+dt@kernel.org, festevam@gmail.com, kernel@pengutronix.de,
        krzysztof.kozlowski+dt@linaro.org, linux-imx@nxp.com,
        mturquette@baylibre.com, peng.fan@nxp.com, robh+dt@kernel.org,
        s.hauer@pengutronix.de, shawnguo@kernel.org,
        shengjiu.wang@gmail.com
Date:   Wed, 19 Jul 2023 13:17:02 -0700
User-Agent: alot/0.10
Precedence: bulk

Quoting Shengjiu Wang (2023-07-14 01:10:59)
> diff --git a/drivers/clk/imx/clk-imx8-acm.c b/drivers/clk/imx/clk-imx8-ac=
m.c
> new file mode 100644
> index 000000000000..445a0b38281c
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imx8-acm.c
> @@ -0,0 +1,477 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +//
> +// Copyright 2023 NXP
> +//
> +
> +#include <dt-bindings/clock/imx8-clock.h>
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/slab.h>
> +
> +#include "clk.h"
> +
> +/**
> + * struct clk_imx_acm_pm_domains: structure for multi power domain
> + * @pd_dev: power domain device
> + * @pd_dev_link: power domain device link
> + * @num_domains: power domain nummber
> + */
> +struct clk_imx_acm_pm_domains {
> +       struct device **pd_dev;
> +       struct device_link **pd_dev_link;
> +       int    num_domains;
> +};
> +
> +/**
> + * struct clk_imx8_acm_sel: for clock mux
> + * @name: clock name
> + * @clkid: clock id
> + * @parents: clock parents
> + * @num_parents: clock parents number
> + * @reg: register offset
> + * @shift: bit shift in register
> + * @width: bits width
> + */
> +struct clk_imx8_acm_sel {
> +       const char                      *name;
> +       int                             clkid;
> +       const struct clk_parent_data    *parents;       /* For mux */
> +       int                             num_parents;
> +       u32                             reg;
> +       u8                              shift;
> +       u8                              width;
> +};
> +
> +/**
> + * struct imx8_acm_soc_data: soc specific data
> + * @sels: pointer to struct clk_imx8_acm_sel
> + * @num_sels: numbers of items
> + */
> +struct imx8_acm_soc_data {
> +       struct clk_imx8_acm_sel *sels;
> +       unsigned int num_sels;
> +};
> +
> +/**
> + * struct imx8_acm_priv: private structure

Compile with W=3D1 and see that this isn't kerneldoc. Please fix.

> + * @dev_pm: multi power domain
> + * @soc_data: pointer to soc data
> + * @reg: base address of registers
> + * @regs: save registers for suspend
> + */
> +struct imx8_acm_priv {
> +       struct clk_imx_acm_pm_domains dev_pm;
> +       const struct imx8_acm_soc_data *soc_data;
> +       void __iomem *reg;
> +       u32 regs[IMX_ADMA_ACM_CLK_END];
> +};
> +
> +static const struct clk_parent_data imx8qm_aud_clk_sels[] =3D {
> +       {.fw_name =3D "aud_rec_clk0_lpcg_clk", .name =3D "aud_rec_clk0_lp=
cg_clk" },

There should only be fw_name here, or use an index. Presumably this
isn't migrating old code or bindings. Also, please add space after { and
before }.

> +       {.fw_name =3D "aud_rec_clk1_lpcg_clk", .name =3D "aud_rec_clk1_lp=
cg_clk" },
> +       {.fw_name =3D "mlb_clk", .name =3D "mlb_clk" },
> +       {.fw_name =3D "hdmi_rx_mclk", .name =3D "hdmi_rx_mclk" },
> +       {.fw_name =3D "ext_aud_mclk0", .name =3D "ext_aud_mclk0" },
> +       {.fw_name =3D "ext_aud_mclk1", .name =3D "ext_aud_mclk1" },
> +       {.fw_name =3D "esai0_rx_clk", .name =3D "esai0_rx_clk" },
> +       {.fw_name =3D "esai0_rx_hf_clk", .name =3D "esai0_rx_hf_clk" },
> +       {.fw_name =3D "esai0_tx_clk", .name =3D "esai0_tx_clk" },
> +       {.fw_name =3D "esai0_tx_hf_clk", .name =3D "esai0_tx_hf_clk" },
> +       {.fw_name =3D "esai1_rx_clk", .name =3D "esai1_rx_clk" },
> +       {.fw_name =3D "esai1_rx_hf_clk", .name =3D "esai1_rx_hf_clk" },
> +       {.fw_name =3D "esai1_tx_clk", .name =3D "esai1_tx_clk" },
> +       {.fw_name =3D "esai1_tx_hf_clk", .name =3D "esai1_tx_hf_clk" },
> +       {.fw_name =3D "spdif0_rx", .name =3D "spdif0_rx" },
> +       {.fw_name =3D "spdif1_rx", .name =3D "spdif1_rx" },
> +       {.fw_name =3D "sai0_rx_bclk", .name =3D "sai0_rx_bclk" },
> +       {.fw_name =3D "sai0_tx_bclk", .name =3D "sai0_tx_bclk" },
> +       {.fw_name =3D "sai1_rx_bclk", .name =3D "sai1_rx_bclk" },
> +       {.fw_name =3D "sai1_tx_bclk", .name =3D "sai1_tx_bclk" },
> +       {.fw_name =3D "sai2_rx_bclk", .name =3D "sai2_rx_bclk" },
> +       {.fw_name =3D "sai3_rx_bclk", .name =3D "sai3_rx_bclk" },
> +       {.fw_name =3D "sai4_rx_bclk", .name =3D "sai4_rx_bclk" },
> +};
[...]
> +
> +static const struct clk_parent_data imx8dxl_mclk_out_sels[] =3D {
> +       {.fw_name =3D "aud_rec_clk0_lpcg_clk", .name =3D "aud_rec_clk0_lp=
cg_clk" },
> +       {.fw_name =3D "aud_rec_clk1_lpcg_clk", .name =3D "aud_rec_clk1_lp=
cg_clk" },
> +       {.name =3D "dummy" },
> +       {.name =3D "dummy" },
> +       {.fw_name =3D "spdif0_rx", .name =3D "spdif0_rx" },
> +       {.name =3D "dummy" },
> +       {.name =3D "dummy" },
> +       {.name =3D "dummy" },

Instead of dummy can you use -1 as the index?