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From:   Peng Fan <peng.fan@nxp.com>
To:     "Peng Fan (OSS)" <peng.fan@oss.nxp.com>,
        "abelvesa@kernel.org" <abelvesa@kernel.org>,
        "mturquette@baylibre.com" <mturquette@baylibre.com>,
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        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
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CC:     dl-linux-imx <linux-imx@nxp.com>,
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        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Ye Li <ye.li@nxp.com>, Jacky Bai <ping.bai@nxp.com>
Subject: RE: [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range
Thread-Topic: [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range
Thread-Index: AQHZp2CbnGgVjWRZJk2vJ7TPHjeSc6/B/8Kw
Date:   Thu, 20 Jul 2023 01:12:34 +0000
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References: <20230625123340.4067536-1-peng.fan@oss.nxp.com>
In-Reply-To: <20230625123340.4067536-1-peng.fan@oss.nxp.com>
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Hi Abel, Stephen,

> Subject: [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range

Would you give a look at this patchset?

Thanks,
Peng.

>=20
> From: Ye Li <ye.li@nxp.com>
>=20
> The SPLL2 on iMX8ULP is different with other frac PLLs, it can support VC=
O
> from 650Mhz to 1Ghz. According to RM, the MULT is using a range from 27
> to 54, not some fixed values. If using current PLL implementation, some
> clock rate can't be supported.
>=20
> Fix the issue by adding new type for the SPLL2 and use MULT range to
> replace MULT table
>=20
> Fixes: 5f0601c47c33 ("clk: imx: Update the pllv4 to support imx8ulp")
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/imx/clk-pllv4.c | 46 +++++++++++++++++++++++++++++--------
>  drivers/clk/imx/clk.h       |  1 +
>  2 files changed, 37 insertions(+), 10 deletions(-)
>=20
> diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c in=
dex
> 6e7e34571fc8..9b136c951762 100644
> --- a/drivers/clk/imx/clk-pllv4.c
> +++ b/drivers/clk/imx/clk-pllv4.c
> @@ -44,11 +44,15 @@ struct clk_pllv4 {
>  	u32		cfg_offset;
>  	u32		num_offset;
>  	u32		denom_offset;
> +	bool		use_mult_range;
>  };
>=20
>  /* Valid PLL MULT Table */
>  static const int pllv4_mult_table[] =3D {33, 27, 22, 20, 17, 16};
>=20
> +/* Valid PLL MULT range, (max, min) */
> +static const int pllv4_mult_range[] =3D {54, 27};
> +
>  #define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
>=20
>  #define LOCK_TIMEOUT_US		USEC_PER_MSEC
> @@ -94,17 +98,30 @@ static unsigned long clk_pllv4_recalc_rate(struct
> clk_hw *hw,  static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned
> long rate,
>  				 unsigned long *prate)
>  {
> +	struct clk_pllv4 *pll =3D to_clk_pllv4(hw);
>  	unsigned long parent_rate =3D *prate;
>  	unsigned long round_rate, i;
>  	u32 mfn, mfd =3D DEFAULT_MFD;
>  	bool found =3D false;
>  	u64 temp64;
> -
> -	for (i =3D 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> -		round_rate =3D parent_rate * pllv4_mult_table[i];
> -		if (rate >=3D round_rate) {
> +	u32 mult;
> +
> +	if (pll->use_mult_range) {
> +		temp64 =3D (u64)rate;
> +		do_div(temp64, parent_rate);
> +		mult =3D temp64;
> +		if (mult >=3D pllv4_mult_range[1] &&
> +		    mult <=3D pllv4_mult_range[0]) {
> +			round_rate =3D parent_rate * mult;
>  			found =3D true;
> -			break;
> +		}
> +	} else {
> +		for (i =3D 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> +			round_rate =3D parent_rate * pllv4_mult_table[i];
> +			if (rate >=3D round_rate) {
> +				found =3D true;
> +				break;
> +			}
>  		}
>  	}
>=20
> @@ -138,14 +155,20 @@ static long clk_pllv4_round_rate(struct clk_hw
> *hw, unsigned long rate,
>  	return round_rate + (u32)temp64;
>  }
>=20
> -static bool clk_pllv4_is_valid_mult(unsigned int mult)
> +static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int
> +mult)
>  {
>  	int i;
>=20
>  	/* check if mult is in valid MULT table */
> -	for (i =3D 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> -		if (pllv4_mult_table[i] =3D=3D mult)
> +	if (pll->use_mult_range) {
> +		if (mult >=3D pllv4_mult_range[1] &&
> +		    mult <=3D pllv4_mult_range[0])
>  			return true;
> +	} else {
> +		for (i =3D 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
> +			if (pllv4_mult_table[i] =3D=3D mult)
> +				return true;
> +		}
>  	}
>=20
>  	return false;
> @@ -160,7 +183,7 @@ static int clk_pllv4_set_rate(struct clk_hw *hw,
> unsigned long rate,
>=20
>  	mult =3D rate / parent_rate;
>=20
> -	if (!clk_pllv4_is_valid_mult(mult))
> +	if (!clk_pllv4_is_valid_mult(pll, mult))
>  		return -EINVAL;
>=20
>  	if (parent_rate <=3D MAX_MFD)
> @@ -227,10 +250,13 @@ struct clk_hw *imx_clk_hw_pllv4(enum
> imx_pllv4_type type, const char *name,
>=20
>  	pll->base =3D base;
>=20
> -	if (type =3D=3D IMX_PLLV4_IMX8ULP) {
> +	if (type =3D=3D IMX_PLLV4_IMX8ULP ||
> +	    type =3D=3D IMX_PLLV4_IMX8ULP_1GHZ) {
>  		pll->cfg_offset =3D IMX8ULP_PLL_CFG_OFFSET;
>  		pll->num_offset =3D IMX8ULP_PLL_NUM_OFFSET;
>  		pll->denom_offset =3D IMX8ULP_PLL_DENOM_OFFSET;
> +		if (type =3D=3D IMX_PLLV4_IMX8ULP_1GHZ)
> +			pll->use_mult_range =3D true;
>  	} else {
>  		pll->cfg_offset =3D PLL_CFG_OFFSET;
>  		pll->num_offset =3D PLL_NUM_OFFSET;
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index
> af19d9f6aed0..adb7ad649a0d 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -45,6 +45,7 @@ enum imx_pll14xx_type {  enum imx_pllv4_type {
>  	IMX_PLLV4_IMX7ULP,
>  	IMX_PLLV4_IMX8ULP,
> +	IMX_PLLV4_IMX8ULP_1GHZ,
>  };
>=20
>  enum imx_pfdv2_type {
> --
> 2.37.1