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From:   Eric Lin <eric.lin@sifive.com>
To:     robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com,
        will@kernel.org, mark.rutland@arm.com, tglx@linutronix.de,
        peterz@infradead.org, devicetree@vger.kernel.org,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Cc:     zong.li@sifive.com, greentime.hu@sifive.com,
        vincent.chen@sifive.com, Eric Lin <eric.lin@sifive.com>
Subject: [PATCH v2 0/3] Add SiFive Private L2 cache and PMU driver
Date:   Thu, 20 Jul 2023 21:51:18 +0800
Message-Id: <20230720135125.21240-1-eric.lin@sifive.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

This patch series adds the SiFive Private L2 cache controller
driver and Performance Monitoring Unit (PMU) driver.

The Private L2 cache communicates with both the upstream L1
caches and downstream L3 cache or memory, enabling a high-
performance cache subsystem. It is also responsible for managing
requests from the L1 instruction and data caches of the core.

The Private L2 Performance Monitoring Unit (PMU) consists of a
set of event-programmable counters and their event selector registers.
The registers are available to control the behavior of the counters.

Changes since v1:
 - Rebased on Linux-6.5-rc2
 - Change pl2 cache compatible string to lowercase
 - Add cpuhp_remove_state() after pl2 cache driver probe fail
 - Return 0 instead of return ret at the end of sifive_pl2_cache_init()
 - Cut down the pl2 cache config log lines in pl2_config_read()
 - Sorting the variable by types in sifive_pl2_cache_dev_probe()
 - Change the error message when failing to find the CPU node
 - Add pl2 PMU driver to support per-task profile
 - Move the pl2 PMU driver implementation to the drivers/perf folder
 - Keep only one pl2 cache compatible string suggested by Krzysztof and Conor
 - Addressed Krzysztof's and Conor's comments on DT binding

Eric Lin (2):
  dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
  soc: sifive: Add SiFive private L2 cache driver

Greentime Hu (1):
  soc: sifive: Add SiFive private L2 cache PMU driver

 .../bindings/cache/sifive,pl2cache.yaml       |  62 ++
 drivers/perf/Kconfig                          |  10 +
 drivers/perf/Makefile                         |   1 +
 drivers/perf/sifive_pl2_pmu.c                 | 602 ++++++++++++++++++
 drivers/soc/sifive/Kconfig                    |   8 +
 drivers/soc/sifive/Makefile                   |   1 +
 drivers/soc/sifive/sifive_pl2.h               |  29 +
 drivers/soc/sifive/sifive_pl2_cache.c         | 202 ++++++
 include/linux/cpuhotplug.h                    |   1 +
 9 files changed, 916 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
 create mode 100644 drivers/perf/sifive_pl2_pmu.c
 create mode 100644 drivers/soc/sifive/sifive_pl2.h
 create mode 100644 drivers/soc/sifive/sifive_pl2_cache.c

-- 
2.40.1