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References: <20230720131028.3730704-1-james.hilliard1@gmail.com> <20230720131028.3730704-4-james.hilliard1@gmail.com>
In-Reply-To: <20230720131028.3730704-4-james.hilliard1@gmail.com>
From:   Fabio Estevam <festevam@gmail.com>
Date:   Thu, 20 Jul 2023 10:34:21 -0300
Message-ID: <CAOMZO5DZJNummE3fRtZpnrL-2LUWKPn6UsW8HuE_=8r9qAtMjg@mail.gmail.com>
Subject: Re: [PATCH v3 4/4] ARM: dts: imx6q: Add Variscite MX6 Custom board support
To:     James Hilliard <james.hilliard1@gmail.com>
Cc:     devicetree@vger.kernel.org,
        Gregory CLEMENT <gregory.clement@bootlin.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        NXP Linux Team <linux-imx@nxp.com>,
        Marek Vasut <marex@denx.de>,
        Frieder Schrempf <frieder.schrempf@kontron.de>,
        Stefan Wahren <stefan.wahren@chargebyte.com>,
        Tim Harvey <tharvey@gateworks.com>,
        Marcel Ziswiler <marcel.ziswiler@toradex.com>,
        Christoph Niedermaier <cniedermaier@dh-electronics.com>,
        Li Yang <leoyang.li@nxp.com>, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
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On Thu, Jul 20, 2023 at 10:10=E2=80=AFAM James Hilliard
<james.hilliard1@gmail.com> wrote:

> +       reg_audio: regulator-audio {
> +               compatible =3D "regulator-fixed";
> +               regulator-name =3D "tlv320aic3x-supply";
> +               enable-active-high;

There is no gpio associated, so 'enable-active-high' should be removed.

> +       backlight_lvds: backlight-lvds {
> +               compatible =3D "pwm-backlight";
> +               pwms =3D <&pwm2 0 50000 0>;
> +               brightness-levels =3D <0 4 8 16 32 64 128 248>;
> +               default-brightness-level =3D <7>;
> +               power-supply =3D <&reg_pu>;

Is this correct? reg_pu is an internal regulator and should supply the
internal SoC peripherals.

> +       };

> +&iomuxc {
> +       pinctrl_ipu1: ipu1grp {
> +               fsl,pins =3D <
> +                       MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0=
x10
> +                       MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0=
x10
> +                       MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0=
x10
> +                       MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0=
x10
> +                       MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04             0=
x10
> +                       MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0=
x10
> +                       MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0=
x10
> +                       MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0=
x10
> +                       MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0=
x10
> +                       MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0=
x10
> +                       MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0=
x10
> +                       MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0=
x10
> +                       MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0=
x10
> +                       MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0=
x10
> +                       MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0=
x10
> +                       MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22       0=
x10
> +                       MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23       0=
x10
> +               >;
> +       };
> +
> +       pinctrl_ipu1: ipu1grp {

pinctrl_ipu1 appears twice. This second entry should be pinctrl_camera
or something like that.

> +       pinctrl_flexcan1: flexcan1grp {
> +               fsl,pins =3D <
> +                       MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
> +                       MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0

Move pinctrl_flexcan1 to keep the pinctrl entries sorted.

> +
> +&ldb {
> +       status =3D "okay";
> +
> +       lvds-channel@0 {
> +               fsl,data-mapping =3D "spwg";
> +               fsl,data-width =3D <24>;
> +               status =3D "okay";

Add a new line.

> +               port@4 {
> +                       reg =3D <4>;
> +
> +                       lvds0_out: endpoint {
> +                               remote-endpoint =3D <&panel_in_lvds0>;
> +                       };
> +               };
> +       };
> +
> +       lvds-channel@1 {
> +               fsl,data-mapping =3D "spwg";
> +               fsl,data-width =3D <24>;
> +               status =3D "okay";

Add a new line.

> +               port@4 {