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Date:   Thu, 20 Jul 2023 17:16:03 +0200
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Subject: Re: [patch 00/58] x86/apic: Decrapification and static calls
To:     Peter Zijlstra <peterz@infradead.org>
Cc:     Thomas Gleixner <tglx@linutronix.de>, x86@kernel.org,
        LKML <linux-kernel@vger.kernel.org>
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 <20230720131316.GD3569127@hirez.programming.kicks-ass.net>
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From:   Marc Gonzalez <marc.w.gonzalez@free.fr>
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On 20/07/2023 15:13, Peter Zijlstra wrote:

> On Thu, Jul 20, 2023 at 02:43:55PM +0200, Marc Gonzalez wrote:
>
>> # cat /proc/cpuinfo
>> processor       : 0
>> vendor_id       : GenuineIntel
>> cpu family      : 6
>> model           : 28
>> model name      : Intel(R) Atom(TM) CPU CE4150   @ 1.20GHz
>> stepping        : 10
>> microcode       : 0x106
>> cpu MHz         : 1199.885
>> cache size      : 512 KB
>> physical id     : 0
>> siblings        : 2
>> core id         : 0
>> cpu cores       : 1
>> apicid          : 0
>> initial apicid  : 0
>> fdiv_bug        : no
>> f00f_bug        : no
>> coma_bug        : no
>> fpu             : yes
>> fpu_exception   : yes
>> cpuid level     : 10
>> wp              : yes
>> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_perfmon pebs bts cpuid aperfmperf pni dtes64 monitor ds_cpl vmx tm2 ssse3 cx16 xtpr pdcm movbe lahf_lm tpr_shadow vnmi flexpriority vpid dtherm
>> vmx flags       : vnmi flexpriority tsc_offset vtpr vapic
>> bugs            :
>> bogomips        : 2400.76
>> clflush size    : 64
>> cache_alignment : 64
>> address sizes   : 32 bits physical, 48 bits virtual
> 
> But that's a 64bit chip, no? lm, cx16

Hol'up. A 64b chip with 32b physical addresses?
Only for the additional registers then?

https://www.cpu-world.com/CPUs/Atom/Intel-Atom%20CE4150.html
https://www.techpowerup.com/cpu-specs/atom-ce4150.c1440

I'm 99% sure it's running a 32b kernel.
Are you saying a 64b kernel would work?
(Well, there are several binary blobs, so no way.)

Regards