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From:   Tomasz Jeznach <tjeznach@rivosinc.com>
Date:   Thu, 20 Jul 2023 11:00:10 -0700
Message-ID: <CAH2o1u7uAuXsD6+6Dvam4kzQuUj8s98G0sR26_-q31wvSUYZNA@mail.gmail.com>
Subject: Re: [PATCH 06/11] RISC-V: drivers/iommu/riscv: Add command, fault,
 page-req queues
To:     Nick Kossifidis <mick@ics.forth.gr>
Cc:     Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
        Robin Murphy <robin.murphy@arm.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Anup Patel <apatel@ventanamicro.com>,
        Sunil V L <sunilvl@ventanamicro.com>,
        Sebastien Boeuf <seb@rivosinc.com>, iommu@lists.linux.dev,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux@rivosinc.com
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On Wed, Jul 19, 2023 at 8:12=E2=80=AFPM Nick Kossifidis <mick@ics.forth.gr>=
 wrote:
>
> Hello Tomasz,
>
> On 7/19/23 22:33, Tomasz Jeznach wrote:
> > Enables message or wire signal interrupts for PCIe and platforms device=
s.
> >
>
> The description doesn't match the subject nor the patch content (we
> don't jus enable interrupts, we also init the queues).
>
> > +     /* Parse Queue lengts */
> > +     ret =3D of_property_read_u32(pdev->dev.of_node, "cmdq_len", &iomm=
u->cmdq_len);
> > +     if (!ret)
> > +             dev_info(dev, "command queue length set to %i\n", iommu->=
cmdq_len);
> > +
> > +     ret =3D of_property_read_u32(pdev->dev.of_node, "fltq_len", &iomm=
u->fltq_len);
> > +     if (!ret)
> > +             dev_info(dev, "fault/event queue length set to %i\n", iom=
mu->fltq_len);
> > +
> > +     ret =3D of_property_read_u32(pdev->dev.of_node, "priq_len", &iomm=
u->priq_len);
> > +     if (!ret)
> > +             dev_info(dev, "page request queue length set to %i\n", io=
mmu->priq_len);
> > +
> >       dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
> >
>
> We need to add those to the device tree binding doc (or throw them away,
> I thought it would be better to have them as part of the device
> desciption than a module parameter).
>

We can add them as an optional fields to DT.
Alternatively, I've been looking into an option to auto-scale CQ/PQ
based on number of attached devices, but this gets trickier for
hot-pluggable systems. I've added module parameters as a bare-minimum,
but still looking for better solutions.

>
> > +static irqreturn_t riscv_iommu_priq_irq_check(int irq, void *data);
> > +static irqreturn_t riscv_iommu_priq_process(int irq, void *data);
> > +
>
> > +     case RISCV_IOMMU_PAGE_REQUEST_QUEUE:
> > +             q =3D &iommu->priq;
> > +             q->len =3D sizeof(struct riscv_iommu_pq_record);
> > +             count =3D iommu->priq_len;
> > +             irq =3D iommu->irq_priq;
> > +             irq_check =3D riscv_iommu_priq_irq_check;
> > +             irq_process =3D riscv_iommu_priq_process;
> > +             q->qbr =3D RISCV_IOMMU_REG_PQB;
> > +             q->qcr =3D RISCV_IOMMU_REG_PQCSR;
> > +             name =3D "priq";
> > +             break;
>
>
> It makes more sense to add the code for the page request queue in the
> patch that adds ATS/PRI support IMHO. This comment also applies to its
> interrupt handlers below.
>

ack. will do.

>
> > +static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_c=
ommand *cmd,
> > +                                               u64 addr)
> > +{
> > +     cmd->dword0 |=3D RISCV_IOMMU_CMD_IOTINVAL_AV;
> > +     cmd->dword1 =3D addr;
> > +}
> > +
>
> This needs to be (addr >> 2) to match the spec, same as in the iofence
> command.
>

oops. Thanks!

> Regards,
> Nick
>

regards,
- Tomasz