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Thu, 20 Jul 2023 18:31:58 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36KIVvIG004689 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Jul 2023 18:31:57 GMT Received: from hu-bjorande-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 20 Jul 2023 11:31:57 -0700 Date: Thu, 20 Jul 2023 11:31:56 -0700 From: Bjorn Andersson To: Akhil P Oommen CC: Dmitry Baryshkov , Jordan Crouse , , Sean Paul , , Konrad Dybcio , Abhinav Kumar , , , "Nathan Chancellor" , Rob Clark , "Daniel Vetter" , Ricardo Ribalda , "Joel Fernandes (Google)" , David Airlie Subject: Re: [Freedreno] [PATCH] drm/msm: Check for the GPU IOMMU during bind Message-ID: <20230720183156.GA2667611@hu-bjorande-lv.qualcomm.com> References: <20230309222049.4180579-1-jorcrous@amazon.com> <20230707150307.vb4otu5e6hwoadyf@amazon.com> <2xnvyjlwuxft2uk2pirlbvbrg7krcb4alz7yyna72g4t2qrrfm@qtawbelv3n4l> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <2xnvyjlwuxft2uk2pirlbvbrg7krcb4alz7yyna72g4t2qrrfm@qtawbelv3n4l> X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: O4gJFukcmhiEIgTWW-UQ3xNayDMVqJ6b X-Proofpoint-GUID: O4gJFukcmhiEIgTWW-UQ3xNayDMVqJ6b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-20_10,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 impostorscore=0 phishscore=0 lowpriorityscore=0 clxscore=1011 adultscore=0 suspectscore=0 mlxscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307200155 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jul 10, 2023 at 03:20:44AM +0530, Akhil P Oommen wrote: > On Fri, Jul 07, 2023 at 08:27:18PM +0300, Dmitry Baryshkov wrote: > > > > On 07/07/2023 18:03, Jordan Crouse wrote: > > > On Thu, Jul 06, 2023 at 09:55:13PM +0300, Dmitry Baryshkov wrote: > > > > > > > > On 10/03/2023 00:20, Jordan Crouse wrote: > > > > > While booting with amd,imageon on a headless target the GPU probe was > > > > > failing with -ENOSPC in get_pages() from msm_gem.c. > > > > > > > > > > Investigation showed that the driver was using the default 16MB VRAM > > > > > carveout because msm_use_mmu() was returning false since headless devices > > > > > use a dummy parent device. Avoid this by extending the existing is_a2xx > > > > > priv member to check the GPU IOMMU state on all platforms and use that > > > > > check in msm_use_mmu(). > > > > > > > > > > This works for memory allocations but it doesn't prevent the VRAM carveout > > > > > from being created because that happens before we have a chance to check > > > > > the GPU IOMMU state in adreno_bind. > > > > > > > > > > There are a number of possible options to resolve this but none of them are > > > > > very clean. The easiest way is to likely specify vram=0 as module parameter > > > > > on headless devices so that the memory doesn't get wasted. > > > > > > > > This patch was on my plate for quite a while, please excuse me for > > > > taking it so long. > > > > > > No worries. I'm also chasing a bunch of other stuff too. > > > > > > > I see the following problem with the current code. We have two different > > > > instances than can access memory: MDP/DPU and GPU. And each of them can > > > > either have or miss the MMU. > > > > > > > > For some time I toyed with the idea of determining whether the allocated > > > > BO is going to be used by display or by GPU, but then I abandoned it. We > > > > can have display BOs being filled by GPU, so handling it this way would > > > > complicate things a lot. > > > > > > > > This actually rings a tiny bell in my head with the idea of splitting > > > > the display and GPU parts to two different drivers, but I'm not sure > > > > what would be the overall impact. > > > > > > As I now exclusively work on headless devices I would be 100% for this, > > > but I'm sure that our laptop friends might not agree :) > > > > I do not know here. This is probably a question to Rob, as he better > > understands the interaction between GPU and display parts of the userspace. > > I fully support this if it is feasible. > I second this. > In our architecture, display and GPU are completely independent subsystems. > Like Jordan mentioned, there are IOT products without display. And I wouldn't > be surprised if there is a product with just display and uses software rendering. > And we have SA8295P/SA8540P with two MDSS instances and one GPU. Regards, Bjorn