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Message-ID: <8794c997-f371-70f8-2462-a6c677e7308c@starfivetech.com>
Date:   Fri, 21 Jul 2023 14:41:56 +0800
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Subject: Re: [PATCH v8 0/9] Add STG/ISP/VOUT clock and reset drivers for
 StarFive JH7110
To:     Conor Dooley <conor@kernel.org>
CC:     <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
        "Michael Turquette" <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        "Philipp Zabel" <p.zabel@pengutronix.de>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Hal Feng <hal.feng@starfivetech.com>,
        <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
References: <20230713113902.56519-1-xingyu.wu@starfivetech.com>
 <20230720-enjoyment-gestation-adb8baa9aaf1@spud>
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From:   Xingyu Wu <xingyu.wu@starfivetech.com>
In-Reply-To: <20230720-enjoyment-gestation-adb8baa9aaf1@spud>
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On 2023/7/21 0:32, Conor Dooley wrote:
> On Thu, Jul 13, 2023 at 07:38:53PM +0800, Xingyu Wu wrote:
>> This patch serises are base on the basic JH7110 SYSCRG/AONCRG
>> drivers and add new partial clock drivers and reset supports
>> about System-Top-Group(STG), Image-Signal-Process(ISP)
>> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. These
>> clocks and resets could be used by DMA, VIN and Display modules.
>> 
>> Patches 1 and 2 are about the System-Top-Group clock and reset
>> generator(STGCRG) part. The first patch adds docunmentation to
>> describe STG bindings, and the second patch adds clock driver to
>> support STG clocks and resets as auxiliary device for JH7110.
>> 
>> Patches 3 and 4 are about the Image-Signal-Process clock and reset
>> gennerator(ISPCRG) part. The first patch adds docunmentation to
>> describe ISP bindings, and the second patch adds clock driver to
>> support ISP clocks and resets as auxiliary device for JH7110.
>> And ISP clocks should power on and enable the SYSCRG clocks first
>> before registering.
>> 
>> Patches 5 and 6 are about the Video-Output clock and reset
>> generator(VOUTCRG) part. The first patch adds docunmentation to
>> describe VOUT bindings, and the second patch adds clock driver to
>> support VOUT clocks and resets as auxiliary device for JH7110.
>> And VOUT clocks also should power on and enable the SYSCRG clocks
>> first before registering.
>> 
>> Patch 7 adds struct members to support STG/ISP/VOUT resets.

BTW, I found this patch is not in the linux-next or clk-next.
These STG/ISP/VOUT CRG drivers are 'incomplete' without this resets patch.
I don't know what your plans about this patch and I'm just curious on it.

> 
>> Patch 8 adds external clocks which ISP and VOUT clock driver need.
>> Patch 9 adds device node about STGCRG, ISPCRG and VOUTCRG to JH7110 dts.
> 
> b4 did not detect this correctly, but I picked these 2 up too.
> They should be in next tomorrow.

Thanks to you.

> 
> Please let your co-workers know that they should resend anything that I
> didn't sent a thanks email for today, as it failed to apply (eg DMA,
> eMMC).
> 

Okay, I'll let them know and resent these patches.

Best regards,
Xingyu Wu