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Message-ID: <8bb1a42d-2809-04a9-dcdd-45fc91ea1bde@collabora.com>
Date:   Fri, 21 Jul 2023 10:16:44 +0200
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Subject: Re: [PATCH] arm64: dts: mediatek: mt8195: Set DSU PMU status to fail
To:     =?UTF-8?B?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= 
        <nfraprado@collabora.com>,
        Matthias Brugger <matthias.bgg@gmail.com>
Cc:     kernel@collabora.com, Chen-Yu Tsai <wenst@chromium.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Seiya Wang <seiya.wang@mediatek.com>,
        Tinghan Shen <tinghan.shen@mediatek.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org
References: <20230720200753.322133-1-nfraprado@collabora.com>
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From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
In-Reply-To: <20230720200753.322133-1-nfraprado@collabora.com>
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Il 20/07/23 22:07, Nícolas F. R. A. Prado ha scritto:
> The DSU PMU allows monitoring performance events in the DSU cluster,
> which is done by configuring and reading back values from the DSU PMU
> system registers. However, for write-access to be allowed by ELs lower
> than EL3, the EL3 firmware needs to update the setting on the ACTLR3_EL3
> register, as it is disallowed by default.

Typo: ACTLR_EL2, ACTLR_EL3 bit 12 must be set if SCR.NS is 1;
ACTLR_EL3 bit 12 must be set if SCR.NS is 0.

On MT8195 Chromebooks, SCR.NS is 1 - hence ACTLR_EL2/EL3 must have BIT(12) set,
but at least ACTLR_EL2 doesn't have it set.

I haven't verified EL3, but that doesn't matter, since both need to be set.

> 
> That configuration is not done on the firmware used by the MT8195 SoC,
> as a consequence, booting a MT8195-based machine like
> mt8195-cherry-tomato-r2 with CONFIG_ARM_DSU_PMU enabled hangs the kernel
> just as it writes to the CLUSTERPMOVSCLR_EL1 register, since the
> instruction faults to EL3, and BL31 apparently just re-runs the
> instruction over and over.

...at least for this SoC, TF-A's BL31 fault handler loops over the same
instruction forever, hanging the AP...

Regards,
Angelo

> 
> Mark the DSU PMU node in the Devicetree with status "fail", as the
> machine doesn't have a suitable firmware to make use of it from the
> kernel, and allowing its driver to probe would hang the kernel.
> 
> Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board")
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> 
> ---
> 
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 5c670fce1e47..0705d9c3a6a7 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -313,6 +313,7 @@ dsu-pmu {
>   		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
>   		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
>   		       <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
> +		status = "fail";
>   	};
>   
>   	dmic_codec: dmic-codec {