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Message-ID: <fed3bad5-9200-76b2-1d57-092de3ec0394@linaro.org>
Date:   Fri, 21 Jul 2023 14:05:56 +0200
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Subject: Re: [PATCH v6 1/3] dt-bindings: clock: fsl,imx8-acm: Add audio clock
 mux support
To:     Shengjiu Wang <shengjiu.wang@nxp.com>, abelvesa@kernel.org,
        peng.fan@nxp.com, mturquette@baylibre.com, sboyd@kernel.org,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
        kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
        shengjiu.wang@gmail.com
Cc:     linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
References: <1689934137-21430-1-git-send-email-shengjiu.wang@nxp.com>
 <1689934137-21430-2-git-send-email-shengjiu.wang@nxp.com>
Content-Language: en-US
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <1689934137-21430-2-git-send-email-shengjiu.wang@nxp.com>
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Precedence: bulk

On 21/07/2023 12:08, Shengjiu Wang wrote:
> Add the clock dt-binding file for audio clock mux. which
> is the IP for i.MX8QM, i.MX8QXP, i.MX8DXL.
> 
> The Audio clock mux is binded with all the audio IP and audio clocks
> in the subsystem, so need to list the power domain of related clocks
> and IPs. Each clock and IP has a power domain, so there are so many
> power domains.
> 
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> changes in v6:
> - add clocks and clock-names, for using .fw_name in driver, the clocks
>   need to be list in DT.

You did much more. You sneaked some changes and kept my tag.

> 
> changes in v5:
> - none
> 
> changes in v4:
> - add Reviewed-by tag
> 
> changes in v3:
> - change compatible string fron nxp to fsl, align with file name.
> - add commit message for power domains numbers.
> - remove description of power domain
> 
> changes in v2:
> - update the file name to fsl,imx8-acm.yaml
> - remove "binding" in title
> - add power domains list
> - change the node name in example
> - change to lower-case for hex
> 
>  .../bindings/clock/fsl,imx8-acm.yaml          | 329 ++++++++++++++++++
>  1 file changed, 329 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml b/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml
> new file mode 100644
> index 000000000000..4274c5410c3a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml
> @@ -0,0 +1,329 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX8 Audio Clock Mux
> +
> +maintainers:
> +  - Shengjiu Wang <shengjiu.wang@nxp.com>
> +
> +description: |
> +  NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP
> +  used to control Audio related clock on the SoC.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,imx8qm-acm
> +      - fsl,imx8qxp-acm
> +      - fsl,imx8dxl-acm

Keep alphabetical order.

> +
> +  reg:
> +    maxItems: 1
> +
> +  power-domains:
> +    minItems: 13
> +    maxItems: 21
> +
> +  '#clock-cells':
> +    const: 1
> +    description:
> +      The clock consumer should specify the desired clock by having the clock
> +      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h
> +      for the full list of i.MX8 ACM clock IDs.
> +
> +  clocks:
> +    minItems: 13
> +    maxItems: 27
> +
> +  clock-names:
> +    minItems: 13
> +    maxItems: 27
> +
> +required:
> +  - compatible
> +  - reg
> +  - power-domains
> +  - '#clock-cells'
> +  - clocks
> +  - clock-names
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,imx8qxp-acm
> +    then:
> +      properties:
> +        power-domains:
> +          items:
> +            - description: power domain of IMX_SC_R_AUDIO_CLK_0
> +            - description: power domain of IMX_SC_R_AUDIO_CLK_1
> +            - description: power domain of IMX_SC_R_MCLK_OUT_0
> +            - description: power domain of IMX_SC_R_MCLK_OUT_1
> +            - description: power domain of IMX_SC_R_AUDIO_PLL_0
> +            - description: power domain of IMX_SC_R_AUDIO_PLL_1
> +            - description: power domain of IMX_SC_R_ASRC_0
> +            - description: power domain of IMX_SC_R_ASRC_1
> +            - description: power domain of IMX_SC_R_ESAI_0
> +            - description: power domain of IMX_SC_R_SAI_0
> +            - description: power domain of IMX_SC_R_SAI_1
> +            - description: power domain of IMX_SC_R_SAI_2
> +            - description: power domain of IMX_SC_R_SAI_3
> +            - description: power domain of IMX_SC_R_SAI_4
> +            - description: power domain of IMX_SC_R_SAI_5
> +            - description: power domain of IMX_SC_R_SPDIF_0
> +            - description: power domain of IMX_SC_R_MQS_0
> +
> +        clocks:
> +          minItems: 18
> +          maxItems: 18
> +
> +        clock-names:
> +          items:
> +            - const: aud_rec_clk0_lpcg_clk
> +            - const: aud_rec_clk1_lpcg_clk
> +            - const: aud_pll_div_clk0_lpcg_clk
> +            - const: aud_pll_div_clk1_lpcg_clk
> +            - const: ext_aud_mclk0
> +            - const: ext_aud_mclk1
> +            - const: esai0_rx_clk
> +            - const: esai0_rx_hf_clk
> +            - const: esai0_tx_clk
> +            - const: esai0_tx_hf_clk
> +            - const: spdif0_rx
> +            - const: sai0_rx_bclk
> +            - const: sai0_tx_bclk
> +            - const: sai1_rx_bclk
> +            - const: sai1_tx_bclk
> +            - const: sai2_rx_bclk
> +            - const: sai3_rx_bclk
> +            - const: sai4_rx_bclk
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,imx8qm-acm
> +    then:
> +      properties:
> +        power-domains:
> +          items:
> +            - description: power domain of IMX_SC_R_AUDIO_CLK_0
> +            - description: power domain of IMX_SC_R_AUDIO_CLK_1
> +            - description: power domain of IMX_SC_R_MCLK_OUT_0
> +            - description: power domain of IMX_SC_R_MCLK_OUT_1
> +            - description: power domain of IMX_SC_R_AUDIO_PLL_0
> +            - description: power domain of IMX_SC_R_AUDIO_PLL_1
> +            - description: power domain of IMX_SC_R_ASRC_0
> +            - description: power domain of IMX_SC_R_ASRC_1
> +            - description: power domain of IMX_SC_R_ESAI_0
> +            - description: power domain of IMX_SC_R_ESAI_1
> +            - description: power domain of IMX_SC_R_SAI_0
> +            - description: power domain of IMX_SC_R_SAI_1
> +            - description: power domain of IMX_SC_R_SAI_2
> +            - description: power domain of IMX_SC_R_SAI_3
> +            - description: power domain of IMX_SC_R_SAI_4
> +            - description: power domain of IMX_SC_R_SAI_5
> +            - description: power domain of IMX_SC_R_SAI_6
> +            - description: power domain of IMX_SC_R_SAI_7
> +            - description: power domain of IMX_SC_R_SPDIF_0
> +            - description: power domain of IMX_SC_R_SPDIF_1
> +            - description: power domain of IMX_SC_R_MQS_0
> +
> +        clocks:
> +          minItems: 27
> +          maxItems: 27
> +
> +        clock-names:
> +          items:
> +            - const: aud_rec_clk0_lpcg_clk
> +            - const: aud_rec_clk1_lpcg_clk
> +            - const: aud_pll_div_clk0_lpcg_clk
> +            - const: aud_pll_div_clk1_lpcg_clk
> +            - const: mlb_clk
> +            - const: hdmi_rx_mclk
> +            - const: ext_aud_mclk0
> +            - const: ext_aud_mclk1
> +            - const: esai0_rx_clk
> +            - const: esai0_rx_hf_clk
> +            - const: esai0_tx_clk
> +            - const: esai0_tx_hf_clk
> +            - const: esai1_rx_clk
> +            - const: esai1_rx_hf_clk
> +            - const: esai1_tx_clk
> +            - const: esai1_tx_hf_clk
> +            - const: spdif0_rx
> +            - const: spdif1_rx
> +            - const: sai0_rx_bclk
> +            - const: sai0_tx_bclk
> +            - const: sai1_rx_bclk
> +            - const: sai1_tx_bclk
> +            - const: sai2_rx_bclk
> +            - const: sai3_rx_bclk
> +            - const: sai4_rx_bclk
> +            - const: sai5_tx_bclk
> +            - const: sai6_rx_bclk
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,imx8dxl-acm
> +    then:
> +      properties:
> +        power-domains:
> +          items:
> +            - description: power domain of IMX_SC_R_AUDIO_CLK_0
> +            - description: power domain of IMX_SC_R_AUDIO_CLK_1
> +            - description: power domain of IMX_SC_R_MCLK_OUT_0
> +            - description: power domain of IMX_SC_R_MCLK_OUT_1
> +            - description: power domain of IMX_SC_R_AUDIO_PLL_0
> +            - description: power domain of IMX_SC_R_AUDIO_PLL_1
> +            - description: power domain of IMX_SC_R_ASRC_0
> +            - description: power domain of IMX_SC_R_SAI_0
> +            - description: power domain of IMX_SC_R_SAI_1
> +            - description: power domain of IMX_SC_R_SAI_2
> +            - description: power domain of IMX_SC_R_SAI_3
> +            - description: power domain of IMX_SC_R_SPDIF_0
> +            - description: power domain of IMX_SC_R_MQS_0
> +
> +        clocks:
> +          minItems: 13
> +          maxItems: 13
> +
> +        clock-names:
> +          items:
> +            - const: aud_rec_clk0_lpcg_clk
> +            - const: aud_rec_clk1_lpcg_clk
> +            - const: aud_pll_div_clk0_lpcg_clk
> +            - const: aud_pll_div_clk1_lpcg_clk
> +            - const: ext_aud_mclk0
> +            - const: ext_aud_mclk1
> +            - const: spdif0_rx
> +            - const: sai0_rx_bclk
> +            - const: sai0_tx_bclk
> +            - const: sai1_rx_bclk
> +            - const: sai1_tx_bclk
> +            - const: sai2_rx_bclk
> +            - const: sai3_rx_bclk
> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock Control Module node:
> +  - |
> +    #include <dt-bindings/clock/imx8-lpcg.h>
> +    #include <dt-bindings/firmware/imx/rsrc.h>
> +
> +    aud_rec0_lpcg: clock-controller@59d00000 {
> +        compatible = "fsl,imx8qxp-lpcg";

How is this related to the binding? How this did appear here?!?!

> +        reg = <0x59d00000 0x10000>;
> +        #clock-cells = <1>;
> +        clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
> +        clock-indices = <IMX_LPCG_CLK_0>;
> +        clock-output-names = "aud_rec_clk0_lpcg_clk";
> +        power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
> +    };

You have way too many examples here. Keep only one relevant. So
definitely not this.

> +
> +    aud_rec1_lpcg: clock-controller@59d10000 {
> +        compatible = "fsl,imx8qxp-lpcg";
> +        reg = <0x59d10000 0x10000>;
> +        #clock-cells = <1>;
> +        clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>;
> +        clock-indices = <IMX_LPCG_CLK_0>;
> +        clock-output-names = "aud_rec_clk1_lpcg_clk";
> +        power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
> +    };

Not this.

> +
> +    aud_pll_div0_lpcg: clock-controller@59d20000 {
> +        compatible = "fsl,imx8qxp-lpcg";
> +        reg = <0x59d20000 0x10000>;
> +        #clock-cells = <1>;
> +        clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>;
> +        clock-indices = <IMX_LPCG_CLK_0>;
> +        clock-output-names = "aud_pll_div_clk0_lpcg_clk";
> +        power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;

Not this.

> +    };
> +
> +    aud_pll_div1_lpcg: clock-controller@59d30000 {
> +        compatible = "fsl,imx8qxp-lpcg";
> +        reg = <0x59d30000 0x10000>;
> +        #clock-cells = <1>;
> +        clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>;
> +        clock-indices = <IMX_LPCG_CLK_0>;
> +        clock-output-names = "aud_pll_div_clk1_lpcg_clk";
> +        power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;

Not this.

> +    };
> +
> +    clk_dummy: clock-dummy {
> +        compatible = "fixed-clock";
> +        #clock-cells = <0>;
> +        clock-frequency = <0>;
> +        clock-output-names = "clk_dummy";
> +    };

drop, not related.

> +
> +    clock-controller@59e00000 {
> +        compatible = "fsl,imx8qxp-acm";

Finally, this one looks relevant.


Best regards,
Krzysztof