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From:   Raghavendra Rao Ananta <rananta@google.com>
Date:   Mon, 24 Jul 2023 09:47:46 -0700
Message-ID: <CAJHc60znT5ThqKE3TgTW-0Us3oNv8+KF=81TSK0PbG3tTyJLFQ@mail.gmail.com>
Subject: Re: [PATCH v7 12/12] KVM: arm64: Use TLBI range-based intructions for unmap
To:     Shaoqin Huang <shahuang@redhat.com>
Cc:     Oliver Upton <oliver.upton@linux.dev>,
        Marc Zyngier <maz@kernel.org>,
        James Morse <james.morse@arm.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Paolo Bonzini <pbonzini@redhat.com>,
        Sean Christopherson <seanjc@google.com>,
        Huacai Chen <chenhuacai@kernel.org>,
        Zenghui Yu <yuzenghui@huawei.com>,
        Anup Patel <anup@brainfault.org>,
        Atish Patra <atishp@atishpatra.org>,
        Jing Zhang <jingzhangos@google.com>,
        Reiji Watanabe <reijiw@google.com>,
        Colton Lewis <coltonlewis@google.com>,
        David Matlack <dmatlack@google.com>,
        linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
        linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        kvm@vger.kernel.org
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On Mon, Jul 24, 2023 at 2:35=E2=80=AFAM Shaoqin Huang <shahuang@redhat.com>=
 wrote:
>
> Hi Raghavendra,
>
> On 7/22/23 10:22, Raghavendra Rao Ananta wrote:
> > The current implementation of the stage-2 unmap walker traverses
> > the given range and, as a part of break-before-make, performs
> > TLB invalidations with a DSB for every PTE. A multitude of this
> > combination could cause a performance bottleneck on some systems.
> >
> > Hence, if the system supports FEAT_TLBIRANGE, defer the TLB
> > invalidations until the entire walk is finished, and then
> > use range-based instructions to invalidate the TLBs in one go.
> > Condition deferred TLB invalidation on the system supporting FWB,
> > as the optimization is entirely pointless when the unmap walker
> > needs to perform CMOs.
> >
> > Rename stage2_put_pte() to stage2_unmap_put_pte() as the function
> > now serves the stage-2 unmap walker specifically, rather than
> > acting generic.
> >
> > Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> > ---
> >   arch/arm64/kvm/hyp/pgtable.c | 67 +++++++++++++++++++++++++++++++----=
-
> >   1 file changed, 58 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.=
c
> > index 5ef098af1736..cf88933a2ea0 100644
> > --- a/arch/arm64/kvm/hyp/pgtable.c
> > +++ b/arch/arm64/kvm/hyp/pgtable.c
> > @@ -831,16 +831,54 @@ static void stage2_make_pte(const struct kvm_pgta=
ble_visit_ctx *ctx, kvm_pte_t n
> >       smp_store_release(ctx->ptep, new);
> >   }
> >
> > -static void stage2_put_pte(const struct kvm_pgtable_visit_ctx *ctx, st=
ruct kvm_s2_mmu *mmu,
> > -                        struct kvm_pgtable_mm_ops *mm_ops)
> > +struct stage2_unmap_data {
> > +     struct kvm_pgtable *pgt;
> > +     bool defer_tlb_flush_init;
> > +};
> > +
> > +static bool __stage2_unmap_defer_tlb_flush(struct kvm_pgtable *pgt)
> > +{
> > +     /*
> > +      * If FEAT_TLBIRANGE is implemented, defer the individual
> > +      * TLB invalidations until the entire walk is finished, and
> > +      * then use the range-based TLBI instructions to do the
> > +      * invalidations. Condition deferred TLB invalidation on the
> > +      * system supporting FWB, as the optimization is entirely
> > +      * pointless when the unmap walker needs to perform CMOs.
> > +      */
> > +     return system_supports_tlb_range() && stage2_has_fwb(pgt);
> > +}
> > +
> > +static bool stage2_unmap_defer_tlb_flush(struct stage2_unmap_data *unm=
ap_data)
> > +{
> > +     bool defer_tlb_flush =3D __stage2_unmap_defer_tlb_flush(unmap_dat=
a->pgt);
> > +
> > +     /*
> > +      * Since __stage2_unmap_defer_tlb_flush() is based on alternative
> > +      * patching and the TLBIs' operations behavior depend on this,
> > +      * track if there's any change in the state during the unmap sequ=
ence.
> > +      */
> > +     WARN_ON(unmap_data->defer_tlb_flush_init !=3D defer_tlb_flush);
> > +     return defer_tlb_flush;
> > +}
> > +
> > +static void stage2_unmap_put_pte(const struct kvm_pgtable_visit_ctx *c=
tx,
> > +                             struct kvm_s2_mmu *mmu,
> > +                             struct kvm_pgtable_mm_ops *mm_ops)
> >   {
> > +     struct stage2_unmap_data *unmap_data =3D ctx->arg;
> > +
> >       /*
> > -      * Clear the existing PTE, and perform break-before-make with
> > -      * TLB maintenance if it was valid.
> > +      * Clear the existing PTE, and perform break-before-make if it wa=
s
> > +      * valid. Depending on the system support, the TLB maintenance fo=
r
> > +      * the same can be deferred until the entire unmap is completed.
> >        */
> >       if (kvm_pte_valid(ctx->old)) {
> >               kvm_clear_pte(ctx->ptep);
> > -             kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu, ctx->addr, ct=
x->level);
> > +
> > +             if (!stage2_unmap_defer_tlb_flush(unmap_data))
> Why not directly check (unmap_data->defer_tlb_flush_init) here?
>
(Re-sending the reply as the previous one was formatted as HTML and
was blocked by many lists)

No particular reason per say, but I was just going with the logic of
determining if we need to defer the flush and the WARN_ON() parts
separate.
Any advantage if we directly check in stage2_unmap_put_pte() that I
missed or is this purely for readability?

> > +                     kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, mmu,
> > +                                     ctx->addr, ctx->level);
> Small indent hint. The ctx->addr can align with __kvm_tlb_flush_vmid_ipa.
>
Ah, yes. I'll adjust this if I send out a v8.

Thank you.
Raghavendra
> Thanks,
> Shaoqin
> >       }
> >
> >       mm_ops->put_page(ctx->ptep);
> > @@ -1070,7 +1108,8 @@ int kvm_pgtable_stage2_set_owner(struct kvm_pgtab=
le *pgt, u64 addr, u64 size,
> >   static int stage2_unmap_walker(const struct kvm_pgtable_visit_ctx *ct=
x,
> >                              enum kvm_pgtable_walk_flags visit)
> >   {
> > -     struct kvm_pgtable *pgt =3D ctx->arg;
> > +     struct stage2_unmap_data *unmap_data =3D ctx->arg;
> > +     struct kvm_pgtable *pgt =3D unmap_data->pgt;
> >       struct kvm_s2_mmu *mmu =3D pgt->mmu;
> >       struct kvm_pgtable_mm_ops *mm_ops =3D ctx->mm_ops;
> >       kvm_pte_t *childp =3D NULL;
> > @@ -1098,7 +1137,7 @@ static int stage2_unmap_walker(const struct kvm_p=
gtable_visit_ctx *ctx,
> >        * block entry and rely on the remaining portions being faulted
> >        * back lazily.
> >        */
> > -     stage2_put_pte(ctx, mmu, mm_ops);
> > +     stage2_unmap_put_pte(ctx, mmu, mm_ops);
> >
> >       if (need_flush && mm_ops->dcache_clean_inval_poc)
> >               mm_ops->dcache_clean_inval_poc(kvm_pte_follow(ctx->old, m=
m_ops),
> > @@ -1112,13 +1151,23 @@ static int stage2_unmap_walker(const struct kvm=
_pgtable_visit_ctx *ctx,
> >
> >   int kvm_pgtable_stage2_unmap(struct kvm_pgtable *pgt, u64 addr, u64 s=
ize)
> >   {
> > +     int ret;
> > +     struct stage2_unmap_data unmap_data =3D {
> > +             .pgt =3D pgt,
> > +             .defer_tlb_flush_init =3D __stage2_unmap_defer_tlb_flush(=
pgt),
> > +     };
> >       struct kvm_pgtable_walker walker =3D {
> >               .cb     =3D stage2_unmap_walker,
> > -             .arg    =3D pgt,
> > +             .arg    =3D &unmap_data,
> >               .flags  =3D KVM_PGTABLE_WALK_LEAF | KVM_PGTABLE_WALK_TABL=
E_POST,
> >       };
> >
> > -     return kvm_pgtable_walk(pgt, addr, size, &walker);
> > +     ret =3D kvm_pgtable_walk(pgt, addr, size, &walker);
> > +     if (stage2_unmap_defer_tlb_flush(&unmap_data))
> > +             /* Perform the deferred TLB invalidations */
> > +             kvm_tlb_flush_vmid_range(pgt->mmu, addr, size);
> > +
> > +     return ret;
> >   }
> >
> >   struct stage2_attr_data {
>
> --
> Shaoqin
>