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From:   Sami Tolvanen <samitolvanen@google.com>
Date:   Mon, 24 Jul 2023 10:03:14 -0700
Message-ID: <CABCJKufYj6E8WagP5GyB3M_=WfA4H0d=MMxX6+DQg0F8qjNTcQ@mail.gmail.com>
Subject: Re: [PATCH v2] riscv: VMAP_STACK overflow detection thread-safe
To:     Guo Ren <guoren@kernel.org>
Cc:     Deepak Gupta <debug@rivosinc.com>, palmer@dabbelt.com,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
        Jisheng Zhang <jszhang@kernel.org>
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On Thu, Jul 20, 2023 at 8:10=E2=80=AFAM Guo Ren <guoren@kernel.org> wrote:
>
> On Thu, Nov 24, 2022 at 5:48=E2=80=AFPM Deepak Gupta <debug@rivosinc.com>=
 wrote:
> > +.macro asm_per_cpu dst sym tmp
> > +       REG_L \tmp, TASK_TI_CPU_NUM(tp)
> > +       slli  \tmp, \tmp, PER_CPU_OFFSET_SHIFT
> > +       la    \dst, __per_cpu_offset
> > +       add   \dst, \dst, \tmp
> > +       REG_L \tmp, 0(\dst)
> > +       la    \dst, \sym
> > +       add   \dst, \dst, \tmp
> > +.endm
> It's a tricky implementation, and we can't maintain it here because it
> depends on percpu design.

I can certainly understand this concern, but AFAICT this part of the
percpu code hasn't changed in ~14 years, so adding an assembly macro
for the computation shouldn't be a huge maintenance burden. arm64 also
performs a similar computation in assembly (starting with commit
3d8c1a013d78) and I don't see their implementation needing constant
maintenance since then.

Sami