Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
References: <20230722113445.630714-1-alexghiti@rivosinc.com>
 <20230722113445.630714-2-alexghiti@rivosinc.com> <b0826064-0cd6-dfd0-a377-5cd56c4035be@infradead.org>
In-Reply-To: <b0826064-0cd6-dfd0-a377-5cd56c4035be@infradead.org>
From:   Alexandre Ghiti <alexghiti@rivosinc.com>
Date:   Tue, 25 Jul 2023 09:35:04 +0200
Message-ID: <CAHVXubg_gGqLnoCaQCLe4SgS4eVT0rqSTC1DHc+-CEmifH6V6Q@mail.gmail.com>
Subject: Re: [PATCH v5 2/3] Documentation: riscv: Add early boot document
To:     Randy Dunlap <rdunlap@infradead.org>
Cc:     Jonathan Corbet <corbet@lwn.net>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@rivosinc.com>,
        Andrew Jones <ajones@ventanamicro.com>,
        Conor Dooley <conor.dooley@microchip.com>,
        Sunil V L <sunilvl@ventanamicro.com>,
        Song Shuai <songshuaishuai@tinylab.org>,
        linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@rivosinc.com>,
        Atish Patra <atishp@rivosinc.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Precedence: bulk

Hi Randy,

On Sat, Jul 22, 2023 at 10:19=E2=80=AFPM Randy Dunlap <rdunlap@infradead.or=
g> wrote:
>
> Hi,
>
> On 7/22/23 04:34, Alexandre Ghiti wrote:
> > This document describes the constraints and requirements of the early
> > boot process in a RISC-V kernel.
> >
> > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> > Reviewed-by: Bj=C3=B6rn T=C3=B6pel <bjorn@rivosinc.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> > Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
> > Reviewed-by: Atish Patra <atishp@rivosinc.com>
> > Reviewed-by: Song Shuai <songshuaishuai@tinylab.org>
> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> > ---
> > - Changes in v5:
> >   * Rebase on top of docs-next
> >
> >  Documentation/riscv/boot-image-header.rst |   3 -
> >  Documentation/riscv/boot.rst              | 169 ++++++++++++++++++++++
> >  Documentation/riscv/index.rst             |   1 +
> >  3 files changed, 170 insertions(+), 3 deletions(-)
> >  create mode 100644 Documentation/riscv/boot.rst
> >
>
> > diff --git a/Documentation/riscv/boot.rst b/Documentation/riscv/boot.rs=
t
> > new file mode 100644
> > index 000000000000..f890ac442c91
> > --- /dev/null
> > +++ b/Documentation/riscv/boot.rst
> > @@ -0,0 +1,169 @@
> > +.. SPDX-License-Identifier: GPL-2.0
> > +
> > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > +RISC-V Kernel Boot Requirements and Constraints
> > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > +
> > +:Author: Alexandre Ghiti <alexghiti@rivosinc.com>
> > +:Date: 23 May 2023
> > +
> > +This document describes what the RISC-V kernel expects from bootloader=
s and
> > +firmware, but also the constraints that any developer must have in min=
d when
>
> I would s/but/and/.

Ok I change that, thanks.

>
> > +touching the early boot process. For the purposes of this document, th=
e
> > +``early boot process`` refers to any code that runs before the final v=
irtual
> > +mapping is set up.
> > +
> > +Pre-kernel Requirements and Constraints
> > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > +
> > +The RISC-V kernel expects the following of bootloaders and platform fi=
rmware:
> > +
> > +Register state
> > +--------------
> > +
> > +The RISC-V kernel expects:
> > +
> > +  * ``$a0`` to contain the hartid of the current core.
> > +  * ``$a1`` to contain the address of the devicetree in memory.
> > +
> > +CSR state
> > +---------
> > +
> > +The RISC-V kernel expects:
> > +
> > +  * ``$satp =3D 0``: the MMU, if present, must be disabled.
> > +
> > +Reserved memory for resident firmware
> > +-------------------------------------
> > +
> > +The RISC-V kernel must not map any resident memory, or memory protecte=
d with
> > +PMPs, in the direct mapping, so the firmware must correctly mark those=
 regions
> > +as per the devicetree specification and/or the UEFI specification.
> > +
> > +Kernel location
> > +---------------
> > +
> > +The RISC-V kernel expects to be placed at a PMD boundary (2MB aligned =
for rv64
> > +and 4MB aligned for rv32). Note that the EFI stub will physically relo=
cate the
> > +kernel if that's not the case.
> > +
> > +Hardware description
> > +--------------------
> > +
> > +The firmware can pass either a devicetree or ACPI tables to the RISC-V=
 kernel.
> > +
> > +The devicetree is either passed directly to the kernel from the previo=
us stage
> > +using the ``$a1`` register, or when booting with UEFI, it can be passe=
d using the
> > +EFI configuration table.
> > +
> > +The ACPI tables are passed to the kernel using the EFI configuration t=
able. In
> > +this case, a tiny devicetree is still created by the EFI stub. Please =
refer to
> > +"EFI stub and devicetree" section below for details about this devicet=
ree.
> > +
> > +Kernel entrance
> > +---------------
>
> How about "entry" instead of "entrance"?

I have to admit that I don't have the nuance between both words, if
'entry' is more appropriate, I'll change it.

>
> > +
> > +On SMP systems, there are 2 methods to enter the kernel:
> > +
> > +- ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kern=
el, one hart
> > +  wins a lottery and executes the early boot code while the other hart=
s are
> > +  parked waiting for the initialization to finish. This method is most=
ly used to
> > +  support older firmwares without SBI HSM extension and M-mode RISC-V =
kernel.
> > +- ``Ordered booting``: the firmware releases only one hart that will e=
xecute the
> > +  initialization phase and then will start all other harts using the S=
BI HSM
> > +  extension. The ordered booting method is the preferred booting metho=
d for
> > +  booting the RISC-V kernel because it can support cpu hotplug and kex=
ec.
>
> preferably s/cpu/CPU/

Done!

>
> > +
> > +UEFI
> > +----
>
> [snip]
>
> I can't say how correct the documentation is, but it is well-written
> and has no issues with punctuation, grammar, or spelling AFAICT, so
> you can take this if you want it:
>
> Reviewed-by: Randy Dunlap <rdunlap@infradead.org>

Thanks for the nice comments, @Conor Dooley (and others) really helped!

I'll respin a new version today,

Alex

>
> thanks.
> --
> ~Randy