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Date:   Tue, 25 Jul 2023 20:27:22 +0800
From:   kernel test robot <lkp@intel.com>
To:     Tao Zhang <quic_taozha@quicinc.com>,
        Mathieu Poirier <mathieu.poirier@linaro.org>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Konrad Dybcio <konradybcio@gmail.com>,
        Mike Leach <mike.leach@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk@kernel.org>
Cc:     oe-kbuild-all@lists.linux.dev, Tao Zhang <quic_taozha@quicinc.com>,
        Jinlong Mao <quic_jinlmao@quicinc.com>,
        Leo Yan <leo.yan@linaro.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        Tingwei Zhang <quic_tingweiz@quicinc.com>,
        Yuanfang Zhang <quic_yuanfang@quicinc.com>,
        Trilok Soni <quic_tsoni@quicinc.com>,
        Hao Zhang <quic_hazha@quicinc.com>,
        linux-arm-msm@vger.kernel.org, andersson@kernel.org
Subject: Re: [PATCH v7 09/13] coresight-tpdm: Add nodes for dsb edge control
Message-ID: <202307252010.fbqRILwZ-lkp@intel.com>
References: <1690269353-10829-10-git-send-email-quic_taozha@quicinc.com>
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In-Reply-To: <1690269353-10829-10-git-send-email-quic_taozha@quicinc.com>
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Hi Tao,

kernel test robot noticed the following build warnings:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v6.5-rc3 next-20230725]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Tao-Zhang/coresight-tpdm-Remove-the-unnecessary-lock/20230725-152235
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/1690269353-10829-10-git-send-email-quic_taozha%40quicinc.com
patch subject: [PATCH v7 09/13] coresight-tpdm: Add nodes for dsb edge control
config: arm-randconfig-r003-20230725 (https://download.01.org/0day-ci/archive/20230725/202307252010.fbqRILwZ-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230725/202307252010.fbqRILwZ-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202307252010.fbqRILwZ-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/hwtracing/coresight/coresight-tpdm.c: In function 'dsb_edge_ctrl_val_store':
>> drivers/hwtracing/coresight/coresight-tpdm.c:383:28: warning: variable 'mask' set but not used [-Wunused-but-set-variable]
     383 |         unsigned long val, mask, edge_ctrl;
         |                            ^~~~
   drivers/hwtracing/coresight/coresight-tpdm.c: In function 'dsb_edge_ctrl_mask_store':
>> drivers/hwtracing/coresight/coresight-tpdm.c:449:9: warning: this 'else' clause does not guard... [-Wmisleading-indentation]
     449 |         else
         |         ^~~~
   drivers/hwtracing/coresight/coresight-tpdm.c:451:17: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'else'
     451 |                 drvdata->dsb->edge_ctrl_mask[reg] = set;
         |                 ^~~~~~~


vim +/mask +383 drivers/hwtracing/coresight/coresight-tpdm.c

   368	
   369	/*
   370	 * This function is used to control the edge detection according
   371	 * to the index number that has been set.
   372	 * "edge_ctrl" should be one of the following values.
   373	 * 0 - Rising edge detection
   374	 * 1 - Falling edge detection
   375	 * 2 - Rising and falling edge detection (toggle detection)
   376	 */
   377	static ssize_t dsb_edge_ctrl_val_store(struct device *dev,
   378						struct device_attribute *attr,
   379						const char *buf,
   380						size_t size)
   381	{
   382		struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 > 383		unsigned long val, mask, edge_ctrl;
   384		int reg;
   385	
   386		if ((kstrtoul(buf, 0, &edge_ctrl)) || (edge_ctrl > 0x2))
   387			return -EINVAL;
   388	
   389		spin_lock(&drvdata->spinlock);
   390		/*
   391		 * There are 2 bit per DSB Edge Control line.
   392		 * Thus we have 16 lines in a 32bit word.
   393		 */
   394		reg = EDCR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx);
   395		mask = EDCR_TO_WORD_MASK(drvdata->dsb->edge_ctrl_idx);
   396		val = drvdata->dsb->edge_ctrl[reg];
   397		val &= ~EDCR_TO_WORD_MASK(drvdata->dsb->edge_ctrl_idx);
   398		val |= EDCR_TO_WORD_VAL(edge_ctrl, drvdata->dsb->edge_ctrl_idx);
   399		drvdata->dsb->edge_ctrl[reg] = val;
   400		spin_unlock(&drvdata->spinlock);
   401	
   402		return size;
   403	}
   404	static DEVICE_ATTR_RW(dsb_edge_ctrl_val);
   405	
   406	static ssize_t dsb_edge_ctrl_mask_show(struct device *dev,
   407						    struct device_attribute *attr,
   408						    char *buf)
   409	{
   410		struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
   411		ssize_t size = 0;
   412		unsigned long bytes;
   413		int i;
   414	
   415		spin_lock(&drvdata->spinlock);
   416		for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) {
   417			bytes = sysfs_emit_at(buf, size,
   418					  "Val:0x%x\n", drvdata->dsb->edge_ctrl_mask[i]);
   419			if (bytes <= 0)
   420				break;
   421			size += bytes;
   422		}
   423		spin_unlock(&drvdata->spinlock);
   424		return size;
   425	}
   426	
   427	static ssize_t dsb_edge_ctrl_mask_store(struct device *dev,
   428						     struct device_attribute *attr,
   429						     const char *buf,
   430						     size_t size)
   431	{
   432		struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
   433		unsigned long val;
   434		u32 set;
   435		int reg;
   436	
   437		if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))
   438			return -EINVAL;
   439	
   440		spin_lock(&drvdata->spinlock);
   441		/*
   442		 * There is 1 bit per DSB Edge Control Mark line.
   443		 * Thus we have 32 lines in a 32bit word.
   444		 */
   445		reg = EDCMR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx);
   446		set = drvdata->dsb->edge_ctrl_mask[reg];
   447		if (val)
   448			set |= BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx));
 > 449		else
   450			set &= ~BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx));
   451			drvdata->dsb->edge_ctrl_mask[reg] = set;
   452		spin_unlock(&drvdata->spinlock);
   453	
   454		return size;
   455	}
   456	static DEVICE_ATTR_RW(dsb_edge_ctrl_mask);
   457	

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