Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   wang_yang <wang_yang6662023@163.com>
To:     palmer@dabbelt.com
Cc:     aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org, wang_yang <wang_yang6662023@163.com>,
        Wang Yang <yangwang@nj.iscas.ac.cn>
Subject: [PATCH] RISC-V: Use GCC __builtin_prefetch() to implement prefetch(). GCC's __builtin_prefetch() was introduced a long time ago, all supported GCC versions have it.So this patch is to use it for implementing the prefetch. RISC-V Cache Management Operation instructions has been supported by GCC last year.you can refer to https://github.com/gcc-mirror/gcc/commit/3df3ca9014f94fe4af07444fea19b4ab29ba8e73 It is worth noting that CPU based on RISC-V should support Zicbop extension. This has been already done on other architectures (see the commit: https://github.com/torvalds/linux/commit/0453fb3c528c5eb3483441a466b24a4cb409eec5).
Date:   Wed, 26 Jul 2023 15:42:18 +0800
Message-Id: <20230726074218.32933-1-wang_yang6662023@163.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Signed-off-by: Wang Yang <yangwang@nj.iscas.ac.cn>
---
 arch/riscv/include/asm/processor.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index c950a8d9edef..f16d4c85ca5b 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -70,6 +70,17 @@ extern void start_thread(struct pt_regs *regs,
 
 extern unsigned long __get_wchan(struct task_struct *p);
 
+#define ARCH_HAS_PREFETCH
+static inline void prefetch(const void *ptr)
+{
+	__builtin_prefetch(ptr, 0, 3);
+}
+
+#define ARCH_HAS_PREFETCHW
+static inline void prefetchw(const void *ptr)
+{
+	__builtin_prefetch(ptr, 1, 3);
+}
 
 static inline void wait_for_interrupt(void)
 {
-- 
2.34.1