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From:   Praveenkumar I <quic_ipkumar@quicinc.com>
To:     <mani@kernel.org>, <agross@kernel.org>, <andersson@kernel.org>,
        <konrad.dybcio@linaro.org>, <lpieralisi@kernel.org>,
        <kw@linux.com>, <robh@kernel.org>, <bhelgaas@google.com>,
        <linux-pci@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
CC:     <quic_varada@quicinc.com>, <quic_devipriy@quicinc.com>
Subject: [PATCH v2] PCI: qcom: Set max payload size 256 bytes for IPQ9574
Date:   Wed, 26 Jul 2023 16:12:49 +0530
Message-ID: <20230726104249.534210-1-quic_ipkumar@quicinc.com>
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This patch sets 256 bytes as payload size for IPQ9574. This allows
PCIe RC to use the max payload size when a capable link partner is
connected.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
---
[v2]:
	Dropped cover letter for this patch. Configured the max payload
	in the post_init of IPQ9574 instead for early fixup.

 drivers/pci/controller/dwc/pcie-qcom.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 8ee7c2b5de27..739c0d514a96 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1145,6 +1145,15 @@ static int qcom_pcie_post_init(struct qcom_pcie *pcie)
 
 static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie)
 {
+	struct dw_pcie *pci = pcie->pci;
+	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+	u32 val;
+
+	val = readl(pci->dbi_base + offset + PCI_EXP_DEVCTL);
+	val &= ~PCI_EXP_DEVCTL_PAYLOAD;
+	val |= PCI_EXP_DEVCTL_PAYLOAD_256B;
+	writel(val, pci->dbi_base + offset + PCI_EXP_DEVCTL);
+
 	writel(SLV_ADDR_SPACE_SZ_1_27_0,
 	       pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
 
-- 
2.34.1