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Message-ID: <729dd79e-83aa-0237-1edd-1662a6ae28cd@pengutronix.de>
Date:   Thu, 27 Jul 2023 09:20:10 +0200
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Subject: Re: [PATCH v2] net: stmmac: correct MAC propagation delay
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To:     Richard Cochran <richardcochran@gmail.com>
Cc:     Giuseppe Cavallaro <peppe.cavallaro@st.com>,
        Alexandre Torgue <alexandre.torgue@foss.st.com>,
        Jose Abreu <joabreu@synopsys.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        patchwork-jzi@pengutronix.de, netdev@vger.kernel.org,
        linux-stm32@st-md-mailman.stormreply.com,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        kernel@pengutronix.de, kernel test robot <lkp@intel.com>
References: <20230719-stmmac_correct_mac_delay-v2-1-3366f38ee9a6@pengutronix.de>
 <ZMGIuKVP7BEotbrn@hoboy.vegasvil.org>
From:   Johannes Zink <j.zink@pengutronix.de>
In-Reply-To: <ZMGIuKVP7BEotbrn@hoboy.vegasvil.org>
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Hi Richard,

On 7/26/23 22:57, Richard Cochran wrote:
> On Mon, Jul 24, 2023 at 12:01:31PM +0200, Johannes Zink wrote:
> 
> Earlier versions of the IP core return zero from these...
> 
>> +#define	PTP_TS_INGR_LAT	0x68	/* MAC internal Ingress Latency */
>> +#define	PTP_TS_EGR_LAT	0x6c	/* MAC internal Egress Latency */
> 

good catch. Gonna send a v3 with a check to and set the values for dwmac v5 only.

Best regards
Johannes


> and so...
> 
>> +static void correct_latency(struct stmmac_priv *priv)
>> +{
>> +	void __iomem *ioaddr = priv->ptpaddr;
>> +	u32 reg_tsic, reg_tsicsns;
>> +	u32 reg_tsec, reg_tsecsns;
>> +	u64 scaled_ns;
>> +	u32 val;
>> +
>> +	/* MAC-internal ingress latency */
>> +	scaled_ns = readl(ioaddr + PTP_TS_INGR_LAT);
>> +
>> +	/* See section 11.7.2.5.3.1 "Ingress Correction" on page 4001 of
>> +	 * i.MX8MP Applications Processor Reference Manual Rev. 1, 06/2021
>> +	 */
>> +	val = readl(ioaddr + PTP_TCR);
>> +	if (val & PTP_TCR_TSCTRLSSR)
>> +		/* nanoseconds field is in decimal format with granularity of 1ns/bit */
>> +		scaled_ns = ((u64)NSEC_PER_SEC << 16) - scaled_ns;
>> +	else
>> +		/* nanoseconds field is in binary format with granularity of ~0.466ns/bit */
>> +		scaled_ns = ((1ULL << 31) << 16) -
>> +			DIV_U64_ROUND_CLOSEST(scaled_ns * PSEC_PER_NSEC, 466U);
>> +
>> +	reg_tsic = scaled_ns >> 16;
>> +	reg_tsicsns = scaled_ns & 0xff00;
>> +
>> +	/* set bit 31 for 2's compliment */
>> +	reg_tsic |= BIT(31);
>> +
>> +	writel(reg_tsic, ioaddr + PTP_TS_INGR_CORR_NS);
> 
> here reg_tsic = 0x80000000 for a correction of -2.15 seconds! >
> @Jakub  Can you please revert this patch?
> 
> Thanks,
> Richard
> 
> 

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