Received: by 2002:a05:6358:c692:b0:131:369:b2a3 with SMTP id fe18csp2200342rwb; Thu, 27 Jul 2023 03:52:04 -0700 (PDT) X-Google-Smtp-Source: APBJJlG3qBzZMWjgJM21434v7gdrJt5iP1TnKAGhQtNI0S8I29sxnFH+EwvJqS9+DDMzfYJLQss3 X-Received: by 2002:aa7:c30d:0:b0:521:985d:7314 with SMTP id l13-20020aa7c30d000000b00521985d7314mr2107186edq.18.1690455124423; Thu, 27 Jul 2023 03:52:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690455124; cv=none; d=google.com; s=arc-20160816; b=FKUFd8v0uMylqH7UHME+2NXBA05uBnF0qJR5ykaZewihGi5gboQjwY0DvE1B42Ybd6 iJcS1Pcvig0gUW+Oo0zaBVMbep8nnoOReN3ig6Gqo/3wfeaERAtYKkjKli8uh4IuITYJ VlJOcGtH66KAs6HIYVp/rSEmhMnHDGj0GsGwyR3zYJEhdLr1mSDR3Fv4+1e9BmvbZrm2 9Io8Aq5OSjOx5bcDKBxfFoUXdrQVyO/0nLKifVNiQIPKIE5S28ZkAdRBShFFK6EgZX2j TNnIPmrVjPVt+ZCB5hqekUjS9ocI7D7MLv09RGXS3X+/iUdZgSSQpOJPIxrAoDF+C196 sSZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4Jy7z9ahOeHw8W5iZzBES06RFrJUM0A8E3pIWleulkY=; fh=djell8ixvcyqU/mJ6veJqcbgRwD4nTeRiXMTlgu2sHI=; b=rEVvU6D+ouHxDJN0Ytbd0tCvbUi2a9bTebE5CVjj+RcVwNgNZfy+r63+zYL6khlDG2 1aB080IuXYMRRgR3+PWgYZcrCF0YQnaZ1M1yIqWypq23e0+NWknj+ZXpy1nUVKaoaE8R aqZj7738auNQQCp/CPF4pOd48hOunFN4XSUlhgywakVrsQvO3ZqfM4TxW4HyPbyM0ilS oydPkgjTKhTFZUOCGfHSRLVR7+eKYka78z6lfEiNtVS+10W+b26BpqIyUMNF0Jlp+b8b GF4TaH96I8l23GDVCShwi/2//aNZjeM73gchyRQ9Q/eSnGqY6/5g/lslBaMIjc87Fy8N KWlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=A++MCN9u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ba11-20020a0564021acb00b00522384df47fsi785012edb.319.2023.07.27.03.51.39; Thu, 27 Jul 2023 03:52:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=A++MCN9u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233527AbjG0Jr0 (ORCPT + 99 others); Thu, 27 Jul 2023 05:47:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233023AbjG0Jqy (ORCPT ); Thu, 27 Jul 2023 05:46:54 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E918F3 for ; Thu, 27 Jul 2023 02:46:46 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id AA27B6607155; Thu, 27 Jul 2023 10:46:44 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690451205; bh=jXr0wGpGehE+iesVyt9aBsjAnzI1CbtR4qvojrtKsGU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A++MCN9u1ef/RND/MNztksF0USUk5rsIiO6fbESy7XGsWirgIXCc3CHrQ2VDagW8s uz38GX8k/PQh4FWY7vtZT11HvSUSQ+owKfzsqwuRpzO3z40a4WO+Clv4thLdpFrnrf vsazEwnMBrlLw//coV2+Jtl0NSyog/VOA7WpC6uzNm3We2JUhyTfe0NoLSVGgVpcWn Zg3WpXLE8yyJaAz6j9j9mNW0qFDMd9Hcbg8NWKvmuwytuL+ZVbUA6LyUv0tT3IvSAw 9zyv24UqlGQEiNEuGa/Ug7c1Rly6dVrCnqfQK2SGhfKH9P+zp9hgqqMLten/8nMo0b hHMw4fXCx0HDg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" Subject: [PATCH RESEND v6 08/11] drm/mediatek: gamma: Support multi-bank gamma LUT Date: Thu, 27 Jul 2023 11:46:30 +0200 Message-ID: <20230727094633.22505-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230727094633.22505-1-angelogioacchino.delregno@collabora.com> References: <20230727094633.22505-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Newer Gamma IP have got multiple LUT banks: support specifying the size of the LUT banks and handle bank-switching before programming the LUT in mtk_gamma_set_common() in preparation for adding support for MT8195 and newer SoCs. Suggested-by: Jason-JH.Lin [Angelo: Refactored original commit] Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 74 ++++++++++++++--------- 1 file changed, 47 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 407fb0264b80..f1a0b18b6c1a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -25,6 +25,8 @@ #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) +#define DISP_GAMMA_BANK 0x0100 +#define DISP_GAMMA_BANK_BANK GENMASK(1, 0) #define DISP_GAMMA_LUT 0x0700 #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) @@ -38,6 +40,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_bank_size; u16 lut_size; u8 lut_bits; }; @@ -84,9 +87,10 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; - u16 lut_size; + u16 lut_bank_size, lut_size; u8 lut_bits; - u32 cfg_val, word; + u32 cfg_val, lbank_val, word; + int cur_bank, num_lut_banks; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -94,43 +98,57 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt if (gamma && gamma->data) { lut_diff = gamma->data->lut_diff; + lut_bank_size = gamma->data->lut_bank_size; lut_bits = gamma->data->lut_bits; lut_size = gamma->data->lut_size; } else { lut_diff = false; + lut_bank_size = LUT_SIZE_DEFAULT; lut_bits = LUT_BITS_DEFAULT; lut_size = LUT_SIZE_DEFAULT; } + num_lut_banks = lut_size / lut_bank_size; cfg_val = readl(regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < lut_size; i++) { - struct drm_color_lut diff, hwlut; - - hwlut.red = drm_color_lut_extract(lut[i].red, lut_bits); - hwlut.green = drm_color_lut_extract(lut[i].green, lut_bits); - hwlut.blue = drm_color_lut_extract(lut[i].blue, lut_bits); - - if (!lut_diff || (i % 2 == 0)) { - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); - } else { - diff.red = lut[i].red - lut[i - 1].red; - diff.red = drm_color_lut_extract(diff.red, lut_bits); - - diff.green = lut[i].green - lut[i - 1].green; - diff.green = drm_color_lut_extract(diff.green, lut_bits); - - diff.blue = lut[i].blue - lut[i - 1].blue; - diff.blue = drm_color_lut_extract(diff.blue, lut_bits); - - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + + for (cur_bank = 0; cur_bank < num_lut_banks; cur_bank++) { + + /* Switch gamma bank and set data mode before writing LUT */ + if (num_lut_banks > 1) { + lbank_val = FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + writel(lbank_val, regs + DISP_GAMMA_BANK); + } + + for (i = 0; i < lut_bank_size; i++) { + int n = (cur_bank * lut_bank_size) + i; + struct drm_color_lut diff, hwlut; + + hwlut.red = drm_color_lut_extract(lut[n].red, lut_bits); + hwlut.green = drm_color_lut_extract(lut[n].green, lut_bits); + hwlut.blue = drm_color_lut_extract(lut[n].blue, lut_bits); + + if (!lut_diff || (i % 2 == 0)) { + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } else { + diff.red = lut[n].red - lut[n - 1].red; + diff.red = drm_color_lut_extract(diff.red, lut_bits); + + diff.green = lut[n].green - lut[n - 1].green; + diff.green = drm_color_lut_extract(diff.green, lut_bits); + + diff.blue = lut[n].blue - lut[n - 1].blue; + diff.blue = drm_color_lut_extract(diff.blue, lut_bits); + + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } + writel(word, (lut_base + i * 4)); } - writel(word, (lut_base + i * 4)); } /* Enable the gamma table */ @@ -241,11 +259,13 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .lut_bank_size = 512, .lut_bits = 10, .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { + .lut_bank_size = 512, .lut_bits = 10, .lut_diff = true, .lut_size = 512, -- 2.40.1