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Date:   Thu, 27 Jul 2023 08:20:38 -0700
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Subject: Re: [PATCH v4 13/20] KVM:VMX: Emulate read and write to CET MSRs
From:   Sean Christopherson <seanjc@google.com>
To:     Weijiang Yang <weijiang.yang@intel.com>
Cc:     Chao Gao <chao.gao@intel.com>, pbonzini@redhat.com,
        peterz@infradead.org, john.allen@amd.com, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org, rick.p.edgecombe@intel.com,
        binbin.wu@linux.intel.com
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On Thu, Jul 27, 2023, Weijiang Yang wrote:
>=20
> On 7/27/2023 1:16 PM, Chao Gao wrote:
> > > > > @@ -2402,6 +2417,31 @@ static int vmx_set_msr(struct kvm_vcpu *vc=
pu, struct msr_data *msr_info)
> > > > > 		else
> > > > > 			vmx->pt_desc.guest.addr_a[index / 2] =3D data;
> > > > > 		break;
> > > > > +#define VMX_CET_CONTROL_MASK		(~GENMASK_ULL(9, 6))
> > > > bits9-6 are reserved for both intel and amd. Shouldn't this check b=
e
> > > > done in the common code?
> > > My thinking is, on AMD platform, bit 63:2 is anyway reserved since it=
 doesn't
> > > support IBT,
> > You can only say
> >=20
> > 	bits 5:2 and bits 63:10 are reserved since AMD doens't support IBT.
> >=20
> > bits 9:6 are reserved regardless of the support of IBT.
> >=20
> > > so the checks in common code for AMD is enough, when the execution fl=
ow comes
> > > here,
> > >=20
> > > it should be vmx, and need this additional check.
> > The checks against reserved bits are common for AMD and Intel:
> >=20
> > 1. if SHSTK is supported, bit1:0 are not reserved.
> > 2. if IBT is supported, bit5:2 and bit63:10 are not reserved
> > 3. bit9:6 are always reserved.
> >=20
> > There is nothing specific to Intel.

+1

> So you want the code to be:
>=20
> +#define CET_IBT_MASK_BITS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0 (GENMASK_ULL(5, 2) | GENMASK_ULL(63,
> 10))
>=20
> +#define CET_CTRL_RESERVED_BITS GENMASK(9, 6)
>=20
> +#define CET_SHSTK_MASK_BITSGENMASK(1, 0)
>=20
> +if ((!guest_can_use(vcpu, X86_FEATURE_SHSTK) &&
>=20
> +(data & CET_SHSTK_MASK_BITS)) ||
>=20
> +(!guest_can_use(vcpu, X86_FEATURE_IBT) &&
>=20
> +(data & CET_IBT_MASK_BITS)) ||
>=20
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 (data & CET_CTRL_RESERVED_BITS) )
>=20
> ^^^^^^^^^^^^^^^^^^^^^^^^^

Yes, though I vote to separate each check, e.g.

	if (data & CET_CTRL_RESERVED_BITS)
		return 1;

	if (!guest_can_use(vcpu, X86_FEATURE_SHSTK) && (data & CET_SHSTK_MASK_BITS=
))
		return 1;

	if (!guest_can_use(vcpu, X86_FEATURE_IBT) && (data & CET_IBT_MASK_BITS))
		return 1;

I would expect the code generation to be similar, if not outright identical=
, and
IMO it's easier to quickly understand the flow if each check is a separate =
if-statement.