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From:   Ankit Agrawal <ankita@nvidia.com>
To:     Alex Williamson <alex.williamson@redhat.com>
CC:     Jason Gunthorpe <jgg@nvidia.com>,
        Aniket Agashe <aniketa@nvidia.com>, Neo Jia <cjia@nvidia.com>,
        Kirti Wankhede <kwankhede@nvidia.com>,
        "Tarun Gupta (SW-GPU)" <targupta@nvidia.com>,
        Vikram Sethi <vsethi@nvidia.com>,
        Andy Currid <acurrid@nvidia.com>,
        Alistair Popple <apopple@nvidia.com>,
        John Hubbard <jhubbard@nvidia.com>,
        Dan Williams <danw@nvidia.com>,
        "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 1/1] vfio/nvgpu: Add vfio pci variant module for grace
 hopper
Thread-Topic: [PATCH v5 1/1] vfio/nvgpu: Add vfio pci variant module for grace
 hopper
Thread-Index: AQHZuA0UNBO/J73IH0aqgxgx4YgKL6/OIgWAgACFKcc=
Date:   Fri, 28 Jul 2023 04:36:05 +0000
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References: <20230716174333.8221-1-ankita@nvidia.com>
 <20230727142937.536e7259.alex.williamson@redhat.com>
In-Reply-To: <20230727142937.536e7259.alex.williamson@redhat.com>
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=0A=
>> +static ssize_t nvgrace_gpu_vfio_pci_read(struct vfio_device *core_vdev,=
=0A=
>> +             char __user *buf, size_t count, loff_t *ppos)=0A=
>> +{=0A=
>> +     unsigned int index =3D VFIO_PCI_OFFSET_TO_INDEX(*ppos);=0A=
>> +     struct nvgrace_gpu_vfio_pci_core_device *nvdev =3D container_of(=
=0A=
>> +             core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_d=
evice.vdev);=0A=
>> +     u64 offset =3D *ppos & VFIO_PCI_OFFSET_MASK;=0A=
>> +     u8 val =3D 0xFF;=0A=
>> +     size_t i;=0A=
>> +=0A=
>> +     /*=0A=
>> +      * Only the device memory present on the hardware is mapped, which=
 may=0A=
>> +      * not be power-of-2 aligned. A read to the BAR2 region implies an=
=0A=
>> +      * access outside the available device memory on the hardware.=0A=
>> +      */=0A=
>=0A=
> This is not true, userspace has no requirement to only access BAR2 via=0A=
> mmap.  This should support reads from within the coherent memory area.=0A=
=0A=
Just to confirm, the ask is to just update the comment to reflect the behav=
ior,=0A=
right? (I missed to do that in this posting). Because we do redirect the ca=
ll to=0A=
vfio_pci_core_read() here which will perform the read that is within the de=
vice=0A=
region. The read response to synthesize -1 is only for the range that is ou=
tside=0A=
the device memory region.=0A=
=0A=
>> +     if ((index =3D=3D VFIO_PCI_BAR2_REGION_INDEX) &&=0A=
>> +             (offset >=3D nvdev->mem_length)) {=0A=
>> +             for (i =3D 0; i < count; i++)=0A=
>> +                     if (copy_to_user(buf + i, &val, 1))=0A=
>> +                             return -EFAULT;=0A=
>> +             return count;=0A=
>> +     }=0A=
>> +=0A=
>> +     return vfio_pci_core_read(core_vdev, buf, count, ppos);=0A=
>> +=0A=
>> +}=0A=
>> +=0A=
>> +static ssize_t nvgrace_gpu_vfio_pci_write(struct vfio_device *core_vdev=
,=0A=
>> +             const char __user *buf, size_t count, loff_t *ppos)=0A=
>> +{=0A=
>> +     unsigned int index =3D VFIO_PCI_OFFSET_TO_INDEX(*ppos);=0A=
>> +     struct nvgrace_gpu_vfio_pci_core_device *nvdev =3D container_of(=
=0A=
>> +             core_vdev, struct nvgrace_gpu_vfio_pci_core_device, core_d=
evice.vdev);=0A=
>> +     u64 offset =3D *ppos & VFIO_PCI_OFFSET_MASK;=0A=
>> +=0A=
>> +     /*=0A=
>> +      * Only the device memory present on the hardware is mapped, which=
 may=0A=
>> +      * not be power-of-2 aligned. A write to the BAR2 region implies a=
n=0A=
>> +      * access outside the available device memory on the hardware.=0A=
>> +      */=0A=
>=0A=
> Likewise this should support writes within the coherent memory area.=0A=
> Disabling mmap support in QEMU is useful for tracing device accesses.=0A=
> Thanks,=0A=
>=0A=
> Alex=0A=
=0A=
Same comment as above.=0A=
=0A=
> +     if ((index =3D=3D VFIO_PCI_BAR2_REGION_INDEX) &&=0A=
> +             (offset >=3D nvdev->mem_length))=0A=
> +             return count;=0A=
> +=0A=
> +     return vfio_pci_core_write(core_vdev, buf, count, ppos);=0A=
> +}=0A=