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Message-ID: <cbc0c2d68b950bf984b5cb16ce7fa6d2348940ad.camel@maquefel.me>
Subject: Re: [PATCH v3 07/42] soc: Add SoC driver for Cirrus ep93xx
From:   Nikita Shubin <nikita.shubin@maquefel.me>
To:     Andy Shevchenko <andy.shevchenko@gmail.com>
Cc:     Andy Shevchenko <andy@kernel.org>,
        Alexander Sverdlin <alexander.sverdlin@gmail.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        linux-kernel@vger.kernel.org
Date:   Fri, 28 Jul 2023 13:01:11 +0300
In-Reply-To: <CAHp75VdSaxzU_7A7b=Htph29XA=ZbqUPJ6RJu+HtrSA2EbcXig@mail.gmail.com>
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         <79619e92b70fdb4b324758ddb34f84b3b8963256.camel@maquefel.me>
         <CAHp75VdSaxzU_7A7b=Htph29XA=ZbqUPJ6RJu+HtrSA2EbcXig@mail.gmail.com>
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On Fri, 2023-07-28 at 12:46 +0300, Andy Shevchenko wrote:
> On Fri, Jul 28, 2023 at 12:28=E2=80=AFPM Nikita Shubin
> <nikita.shubin@maquefel.me> wrote:
> >=20
> > Hello Andy!
> >=20
> > On Fri, 2023-07-21 at 17:13 +0300, Andy Shevchenko wrote:
> > > On Thu, Jul 20, 2023 at 02:29:07PM +0300, Nikita Shubin via B4
> > > Relay
> > > wrote:
> > > > From: Nikita Shubin <nikita.shubin@maquefel.me>
> > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 spin_lock_irqsave(&ep93xx_swl=
ock, flags);
> > > > +
> > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 regmap_read(map, EP93XX_SYSCO=
N_DEVCFG, &val);
> > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 val &=3D ~clear_bits;
> > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 val |=3D set_bits;
> > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 regmap_write(map, EP93XX_SYSC=
ON_SWLOCK,
> > > > EP93XX_SWLOCK_MAGICK);
> > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 regmap_write(map, EP93XX_SYSC=
ON_DEVCFG, val);
> > >=20
> > > Is this sequence a must?
> > > I.o.w. can you first supply magic and then update devcfg?
> > >=20
> >=20
> > Unfortunately it is a must to write EP93XX_SYSCON_SWLOCK and only
> > then
> > the next write to swlocked registers will succeed.
>=20
> This doesn't answer my question. Can you first write a magic and then
> _update_ the other register (update means RMW op)?
>=20

I see your point now - citing docs:

"Logic safeguards are included to condition the control signals for
power connection to the matrix to prevent part damage. In addition, a
software lock register is included that must be written with 0xAA
before each register write to change the values of the four switch
matrix control registers."

So reading SHOULDN'T affect the lock.

But as we checked reading also breaks the lock, that's why this looks
so odd, it was done for purpose - i'll check it once again anyway.