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From:   Andy Shevchenko <andy.shevchenko@gmail.com>
Date:   Fri, 28 Jul 2023 12:46:28 +0300
Message-ID: <CAHp75VdSaxzU_7A7b=Htph29XA=ZbqUPJ6RJu+HtrSA2EbcXig@mail.gmail.com>
Subject: Re: [PATCH v3 07/42] soc: Add SoC driver for Cirrus ep93xx
To:     Nikita Shubin <nikita.shubin@maquefel.me>
Cc:     Andy Shevchenko <andy@kernel.org>,
        Alexander Sverdlin <alexander.sverdlin@gmail.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        linux-kernel@vger.kernel.org
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On Fri, Jul 28, 2023 at 12:28=E2=80=AFPM Nikita Shubin
<nikita.shubin@maquefel.me> wrote:
>
> Hello Andy!
>
> On Fri, 2023-07-21 at 17:13 +0300, Andy Shevchenko wrote:
> > On Thu, Jul 20, 2023 at 02:29:07PM +0300, Nikita Shubin via B4 Relay
> > wrote:
> > > From: Nikita Shubin <nikita.shubin@maquefel.me>
> > > +       spin_lock_irqsave(&ep93xx_swlock, flags);
> > > +
> > > +       regmap_read(map, EP93XX_SYSCON_DEVCFG, &val);
> > > +       val &=3D ~clear_bits;
> > > +       val |=3D set_bits;
> > > +       regmap_write(map, EP93XX_SYSCON_SWLOCK,
> > > EP93XX_SWLOCK_MAGICK);
> > > +       regmap_write(map, EP93XX_SYSCON_DEVCFG, val);
> >
> > Is this sequence a must?
> > I.o.w. can you first supply magic and then update devcfg?
> >
>
> Unfortunately it is a must to write EP93XX_SYSCON_SWLOCK and only then
> the next write to swlocked registers will succeed.

This doesn't answer my question. Can you first write a magic and then
_update_ the other register (update means RMW op)?


--=20
With Best Regards,
Andy Shevchenko