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[37.201.119.179]) by smtp.googlemail.com with ESMTPSA id f5-20020a1709064dc500b0098669cc16b2sm2158016ejw.83.2023.07.28.08.08.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 08:08:35 -0700 (PDT) From: Wadim Mueller X-Google-Original-From: Wadim Mueller Cc: Wadim Mueller , Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] SPI-NOR: Add support for Micron mt35x01g Date: Fri, 28 Jul 2023 17:08:09 +0200 Message-Id: <20230728150810.205656-1-wadim.mueller@continental-corporation.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wadim Mueller Currently only the mt35xu512aba and mt35xu02g are supported, support for the 1G version is missing. This patch adds the corresponding entry in the micron_parts structure. Verification and tests were done on a custom NXP S32G2 board with the mt35xu01g qspi nor populated Signed-off-by: Wadim Mueller --- drivers/mtd/spi-nor/micron-st.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 4b919756a205..fe97583547fe 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -166,6 +166,11 @@ static const struct flash_info micron_nor_parts[] = { MFR_FLAGS(USE_FSR) .fixups = &mt35xu512aba_fixups }, + { "mt35xu01g", INFO(0x2c5b1b, 0, 128 * 1024, 1024) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ) + FIXUP_FLAGS(SPI_NOR_4B_OPCODES) + MFR_FLAGS(USE_FSR) + }, { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) -- 2.25.1