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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n2-20020a17090ac68200b00263355e8183si3255791pjt.114.2023.07.28.08.48.02; Fri, 28 Jul 2023 08:48:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="S0/2qOh9"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237369AbjG1Pga (ORCPT + 99 others); Fri, 28 Jul 2023 11:36:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236823AbjG1Pg1 (ORCPT ); Fri, 28 Jul 2023 11:36:27 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E2DD10FA for ; Fri, 28 Jul 2023 08:36:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8EE5362179 for ; Fri, 28 Jul 2023 15:36:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD475C433C8; Fri, 28 Jul 2023 15:36:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690558582; bh=g4K5vq4lPyGBYhqgJJE0//L14vL/7BRJwDrh2+NOlqk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=S0/2qOh9DNQM/zNi5r9udD62Tuu5Uosyrt7S4golN5beku3HBItbqx/hsmFGSsjso /K78hYySn6CsOKCp40tUlRsYRNgEQR/ZSeR3x2gxM6/SvBC/W1YQyj7muSEibPxpt4 9fx5kaG5gptMsk367e7ditSVFDcX2XzKOQai8PgIupG70U0dRp3wNZW74zkoQPzZ/g DdsyYULweQssqFoRfX7p2gW8o4eVxrtPtFqJjxOjm0Ib1hFQBJULx5RV4D8BgBxHCD dMb7FJIYJfoGEcIG/KcIdeYFlcF4Pb77Kzu9Gez3zZTCGgrk3wvZLSiigrkx4o4R2s S/qZhlXIcMYCQ== Date: Fri, 28 Jul 2023 16:36:12 +0100 From: Will Deacon To: "Russell King (Oracle)" Cc: Andrew Halaney , Shenwei Wang , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Shawn Guo , Sascha Hauer , Neil Armstrong , Kevin Hilman , Vinod Koul , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Jerome Brunet , Martin Blumenstingl , Bhupesh Sharma , Nobuhiro Iwamatsu , Simon Horman , Bartosz Golaszewski , Wong Vee Khee , Revanth Kumar Uppala , Jochen Henneberg , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, imx@lists.linux.dev, Frank Li Subject: Re: [PATCH v2 net 2/2] net: stmmac: dwmac-imx: pause the TXC clock in fixed-link Message-ID: <20230728153611.GH21718@willie-the-truck> References: <20230727152503.2199550-1-shenwei.wang@nxp.com> <20230727152503.2199550-3-shenwei.wang@nxp.com> <4govb566nypifbtqp5lcbsjhvoyble5luww3onaa2liinboguf@4kgihys6vhrg> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 28, 2023 at 04:22:19PM +0100, Russell King (Oracle) wrote: > On Thu, Jul 27, 2023 at 01:36:45PM -0500, Andrew Halaney wrote: > > I don't have any documentation for the registers here, and as you can > > see I'm an amateur with respect to memory ordering based on my prior > > comment. > > > > But you: > > > > 1. Read intf_reg_off into variable iface > > 2. Write the RESET_SPEED for the appropriate mode to MAC_CTRL_REG > > 3. wmb() to ensure that write goes through > > I wonder about whether that wmb() is required. If the mapping is > device-like rather than memory-like, the write should be committed > before the read that regmap_update_bits() does according to the ARM > memory model. Maybe a bit of information about where this barrier > has come from would be good, and maybe getting it reviewed by the > arm64 barrier specialist, Will Deacon. :) > > wmb() is normally required to be paired with a rmb(), but we're not > talking about system memory here, so I also wonder whether wmb() is > the correct barrier to use. Yes, I don't think wmb() is the right thing here. If you need to ensure that the write to MAC_CTRL_REG has taken effect, then you'll need to go through some device-specific sequence which probably involves reading something back. If you just need things to arrive in order eventually, the memory type already gives you that. It's also worth pointing out that udelay() isn't necessarily ordered wrt MMIO writes, so that usleep_range() might need some help as well. Non-relaxed MMIO reads, however, _are_ ordered against a subsequent udelay(), so if you add the readback then this might all work out. I gave a (slightly dated) talk about some of this at ELC a while back: https://www.youtube.com/watch?v=i6DayghhA8Q which might help. Will