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[2620:137:e000::1:20]) by mx.google.com with ESMTP id h5-20020a170902f54500b001bb20380bf9si3337826plf.545.2023.07.28.09.52.47; Fri, 28 Jul 2023 09:52:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=f3EScmtD; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232343AbjG1QJi (ORCPT + 99 others); Fri, 28 Jul 2023 12:09:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232586AbjG1QJe (ORCPT ); Fri, 28 Jul 2023 12:09:34 -0400 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-vi1eur04on2041.outbound.protection.outlook.com [40.107.8.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD9FB4236; Fri, 28 Jul 2023 09:09:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=m1HfzQuhOTypRSdQ6ivQR/MEZElb5ELa1uZ0ZM3I7ra8DWEEK+oOqZlJgHgaLKjncKS3JIHbsbTBV+QQk6ORgmgXTg0/o6//UB+fZBjao3X+bnxM94VxPWMxTHa8uZcTyXrpnmj4kTdE8Lm3flwi3Dyh63PLc0yCDKsjNlIs/CRUY61rxO60aJwRHdTtALoHE6L+iKGt8Ku+XeCAr3P2c1VnCplsVTSG1zB4GGEfg33m96jFoETp+cn/jiEcbevdabYbbZjAlJBNd9wdt9SXZKnCdSC6+16VGT8Ns5MUPvYz9tDA+RnPodcKFrsX05XEw+JiQUb44zM2t8rb5PkYXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=A/wtqdeGIhqexDWteR5SbI0NJNB1cbv4zHnDzzYRjRU=; b=A++dVbC5WOMeo1+bJcOJ0syL4VlgpsxHdPBNFulZA2Wk/71bOwfJFtCSg/q+nMp8Xxv8sm1oERpA9ltFQ4hIIkIIB44yZNjAAU91NHOLSOTE0MDQl5xNmfFsZ7/UhjULpP/TygZpHahZ0dqTmJvY07i/ebkykfxW7HkmUTBD56LBQkQ0jZ1s8apLUZmcXuvn8rcY4IZN7OjTy0btxtouup4N6Z6X+oXrw6OFep3YrF7AypteV6siUNLYxXxfvdp3DRl4WYHWIsmzyNSvEYDyWNUQm8pSWNc3xrtN9CUuPV9JOl5W6wTbKkqzQGf0REtcKgiqvrMoEL60l73IXNVTCw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=A/wtqdeGIhqexDWteR5SbI0NJNB1cbv4zHnDzzYRjRU=; b=f3EScmtDMM1oIl96kUADqNdZ9NAE4egDD0MZ/WT0PWJm2Z3tItzgHMurDv9tUaMDJXWSIF4TWXaS0byIvbyjEHD9toWMNgtqhbMPMp0ZOAKJWlZkJhSoCxKxxtgeEGYaH/he2TwU9p0PWms9hNRGkLzmUlabk6MD9PzI9Md3DFU= Received: from PAXPR04MB9185.eurprd04.prod.outlook.com (2603:10a6:102:231::11) by DB8PR04MB6956.eurprd04.prod.outlook.com (2603:10a6:10:11b::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6631.29; Fri, 28 Jul 2023 16:09:29 +0000 Received: from PAXPR04MB9185.eurprd04.prod.outlook.com ([fe80::d4ee:8daa:92f4:9671]) by PAXPR04MB9185.eurprd04.prod.outlook.com ([fe80::d4ee:8daa:92f4:9671%3]) with mapi id 15.20.6631.026; Fri, 28 Jul 2023 16:09:29 +0000 From: Shenwei Wang To: Will Deacon , "Russell King (Oracle)" CC: Andrew Halaney , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Shawn Guo , Sascha Hauer , Neil Armstrong , Kevin Hilman , Vinod Koul , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Pengutronix Kernel Team , Fabio Estevam , dl-linux-imx , Jerome Brunet , Martin Blumenstingl , Bhupesh Sharma , Nobuhiro Iwamatsu , Simon Horman , Bartosz Golaszewski , Wong Vee Khee , Revanth Kumar Uppala , Jochen Henneberg , "netdev@vger.kernel.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-amlogic@lists.infradead.org" , "imx@lists.linux.dev" , Frank Li Subject: RE: [EXT] Re: [PATCH v2 net 2/2] net: stmmac: dwmac-imx: pause the TXC clock in fixed-link Thread-Topic: [EXT] Re: [PATCH v2 net 2/2] net: stmmac: dwmac-imx: pause the TXC clock in fixed-link Thread-Index: AQHZwJ6ZmPtrsmRv9UGenRTta+C4Xq/N8VmAgAFcAoCAAAPhAIAAB8xg Date: Fri, 28 Jul 2023 16:09:29 +0000 Message-ID: References: <20230727152503.2199550-1-shenwei.wang@nxp.com> <20230727152503.2199550-3-shenwei.wang@nxp.com> <4govb566nypifbtqp5lcbsjhvoyble5luww3onaa2liinboguf@4kgihys6vhrg> <20230728153611.GH21718@willie-the-truck> In-Reply-To: <20230728153611.GH21718@willie-the-truck> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9185.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 452117ac-b961-4715-0f83-08db8f8505d5 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Jul 2023 16:09:29.4010 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: H5S7fIKe+uz55onENv08oY2pfS/yShoWc7nClbaxRRiHgklqBAPF1Uniqz0R4TSPTb+h1omgW0EaZbywUb2SgQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6956 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Will Deacon > Sent: Friday, July 28, 2023 10:36 AM > To: Russell King (Oracle) > Cc: Andrew Halaney ; Shenwei Wang > ; David S. Miller ; Eric > Dumazet ; Jakub Kicinski ; Paolo > Abeni ; Maxime Coquelin > ; Shawn Guo ; Sascha > Hauer ; Neil Armstrong ; > Kevin Hilman ; Vinod Koul ; Chen- > Yu Tsai ; Jernej Skrabec ; Samue= l > Holland ; Giuseppe Cavallaro > ; Alexandre Torgue = ; > Jose Abreu ; Pengutronix Kernel Team > ; Fabio Estevam ; dl-linux-imx > ; Jerome Brunet ; Martin > Blumenstingl ; Bhupesh Sharma > ; Nobuhiro Iwamatsu > ; Simon Horman > ; Bartosz Golaszewski > ; Wong Vee Khee ; > Revanth Kumar Uppala ; Jochen Henneberg > ; netdev@vger.kernel.org; linux-stm32@st- > md-mailman.stormreply.com; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; linux-amlogic@lists.infradead.org; imx@lists.linu= x.dev; > Frank Li > Subject: [EXT] Re: [PATCH v2 net 2/2] net: stmmac: dwmac-imx: pause the T= XC > clock in fixed-link > > Caution: This is an external email. Please take care when clicking links = or > opening attachments. When in doubt, report the message using the 'Report = this > email' button > > > On Fri, Jul 28, 2023 at 04:22:19PM +0100, Russell King (Oracle) wrote: > > On Thu, Jul 27, 2023 at 01:36:45PM -0500, Andrew Halaney wrote: > > > I don't have any documentation for the registers here, and as you > > > can see I'm an amateur with respect to memory ordering based on my > > > prior comment. > > > > > > But you: > > > > > > 1. Read intf_reg_off into variable iface > > > 2. Write the RESET_SPEED for the appropriate mode to MAC_CTRL_REG > > > 3. wmb() to ensure that write goes through > > > > I wonder about whether that wmb() is required. If the mapping is > > device-like rather than memory-like, the write should be committed > > before the read that regmap_update_bits() does according to the ARM > > memory model. Maybe a bit of information about where this barrier has > > come from would be good, and maybe getting it reviewed by the > > arm64 barrier specialist, Will Deacon. :) > > > > wmb() is normally required to be paired with a rmb(), but we're not > > talking about system memory here, so I also wonder whether wmb() is > > the correct barrier to use. > > Yes, I don't think wmb() is the right thing here. If you need to ensure t= hat the > write to MAC_CTRL_REG has taken effect, then you'll need to go through so= me > device-specific sequence which probably involves reading something back. = If you > just need things to arrive in order eventually, the memory type already g= ives you > that. > > It's also worth pointing out that udelay() isn't necessarily ordered wrt = MMIO > writes, so that usleep_range() might need some help as well. > Non-relaxed MMIO reads, however, _are_ ordered against a subsequent > udelay(), so if you add the readback then this might all work out. > 1. Write RESET_SPEED 2. Write 0 to MX93_GPR_ENET_QOS_INTF_MODE_MASK 3. usleep_range() 4. Restore MX93_GPR_ENET_QOS_CLK_GEN_EN | iface In the above example, if a readback after step #2 could ensure sufficient t= ime has passed before step #4, the wmb() here should be abandoned. Thanks, Shenwei > I gave a (slightly dated) talk about some of this at ELC a while back: > > https://www.yo/ > utube.com%2Fwatch%3Fv%3Di6DayghhA8Q&data=3D05%7C01%7Cshenwei.wang > %40nxp.com%7C32396fd0396e4e46975f08db8f806680%7C686ea1d3bc2b4c6fa > 92cd99c5c301635%7C0%7C0%7C638261553857503588%7CUnknown%7CTWFp > bGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6 > Mn0%3D%7C3000%7C%7C%7C&sdata=3DX5CQrQEVmUjYafYJ%2BzcnGXI9mhDT% > 2BMzDazGHOcoomas%3D&reserved=3D0 > > which might help. > > Will