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Date:   Sun, 30 Jul 2023 11:04:30 +0800
From:   Shawn Guo <shawnguo@kernel.org>
To:     Bough Chen <haibo.chen@nxp.com>
Cc:     "Peng Fan (OSS)" <peng.fan@oss.nxp.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "krzysztof.kozlowski+dt@linaro.org" 
        <krzysztof.kozlowski+dt@linaro.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        dl-linux-imx <linux-imx@nxp.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Sherry Sun <sherry.sun@nxp.com>, Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz pinctrl
 setting for eMMC
Message-ID: <20230730030430.GT151430@dragon>
References: <20230625124238.4071717-1-peng.fan@oss.nxp.com>
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On Mon, Jul 24, 2023 at 06:51:17AM +0000, Bough Chen wrote:
> > -----Original Message-----
> > From: Shawn Guo <shawnguo@kernel.org>
> > Sent: 2023年7月18日 11:32
> > To: Peng Fan (OSS) <peng.fan@oss.nxp.com>
> > Cc: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> > s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com;
> > dl-linux-imx <linux-imx@nxp.com>; devicetree@vger.kernel.org;
> > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Bough
> > Chen <haibo.chen@nxp.com>; Sherry Sun <sherry.sun@nxp.com>; Peng Fan
> > <peng.fan@nxp.com>
> > Subject: Re: [PATCH 09/10] arm64: dts: imx8ulp-evk: add 100MHz/200MHz
> > pinctrl setting for eMMC
> > 
> > On Sun, Jun 25, 2023 at 08:42:37PM +0800, Peng Fan (OSS) wrote:
> > > From: Haibo Chen <haibo.chen@nxp.com>
> > >
> > > Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus
> > > mode to config the eMMC work at HS400ES mode.
> > >
> > > Also update to use Standard Drive Strength for USDHC pad to get a
> > > better signal quality per Hardware team suggests.
> > >
> > > Reviewed-by: Sherry Sun <sherry.sun@nxp.com>
> > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > >  arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 26
> > > ++++++++++---------
> > >  1 file changed, 14 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > index e459dc35e469..ab7af705bbca 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > > @@ -121,9 +121,11 @@ &lpuart5 {
> > >  };
> > >
> > >  &usdhc0 {
> > > -	pinctrl-names = "default", "sleep";
> > > +	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> > >  	pinctrl-0 = <&pinctrl_usdhc0>;
> > >  	pinctrl-1 = <&pinctrl_usdhc0>;
> > > +	pinctrl-2 = <&pinctrl_usdhc0>;
> > > +	pinctrl-3 = <&pinctrl_usdhc0>;
> > 
> > All three speed modes use the same pinctrl?
> 
> Yes, the IOMUX on imx8ulp do not support config different drive strength. So here use the same pinctrl.

Mention that in the commit log or with a comment would be helpful.

Shawn