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Message-ID: <3d4d9b22-8451-f4d5-bbd8-117988f3a545@ics.forth.gr>
Date:   Mon, 31 Jul 2023 12:32:38 +0300
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Subject: Re: [PATCH 06/11] RISC-V: drivers/iommu/riscv: Add command, fault,
 page-req queues
To:     Zong Li <zong.li@sifive.com>,
        Tomasz Jeznach <tjeznach@rivosinc.com>
Cc:     Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
        Robin Murphy <robin.murphy@arm.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Anup Patel <apatel@ventanamicro.com>,
        Albert Ou <aou@eecs.berkeley.edu>, linux@rivosinc.com,
        linux-kernel@vger.kernel.org, Sebastien Boeuf <seb@rivosinc.com>,
        iommu@lists.linux.dev, Palmer Dabbelt <palmer@dabbelt.com>,
        linux-riscv@lists.infradead.org
References: <cover.1689792825.git.tjeznach@rivosinc.com>
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 <CANXhq0pm+1yXuvUGudwNtvNHWV3FytH4VfCnq7_Ws=t-MZP_kQ@mail.gmail.com>
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From:   Nick Kossifidis <mick@ics.forth.gr>
In-Reply-To: <CANXhq0pm+1yXuvUGudwNtvNHWV3FytH4VfCnq7_Ws=t-MZP_kQ@mail.gmail.com>
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On 7/29/23 15:58, Zong Li wrote:
> On Thu, Jul 20, 2023 at 3:34 AM Tomasz Jeznach <tjeznach@rivosinc.com> wrote:
>> +       iommu->cap = riscv_iommu_readq(iommu, RISCV_IOMMU_REG_CAP);
>> +
>> +       /* For now we only support WSIs until we have AIA support */
> 
> I'm not completely understand AIA support here, because I saw the pci
> case uses the MSI, and kernel seems to have the AIA implementation.
> Could you please elaborate it?
> 

When I wrote this we didn't have AIA in the kernel, and without IMSIC we 
can't have MSIs in the hart (we can still have MSIs in the PCIe controller).

> 
> Should we define the "interrupt-names" in dt-bindings?
> 

Yes we should, along with queue lengths below.

>> +
>> +       /* Make sure fctl.WSI is set */
>> +       fctl = riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL);
>> +       fctl |= RISCV_IOMMU_FCTL_WSI;
>> +       riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FCTL, fctl);
>> +
>> +       /* Parse Queue lengts */
>> +       ret = of_property_read_u32(pdev->dev.of_node, "cmdq_len", &iommu->cmdq_len);
>> +       if (!ret)
>> +               dev_info(dev, "command queue length set to %i\n", iommu->cmdq_len);
>> +
>> +       ret = of_property_read_u32(pdev->dev.of_node, "fltq_len", &iommu->fltq_len);
>> +       if (!ret)
>> +               dev_info(dev, "fault/event queue length set to %i\n", iommu->fltq_len);
>> +
>> +       ret = of_property_read_u32(pdev->dev.of_node, "priq_len", &iommu->priq_len);
>> +       if (!ret)
>> +               dev_info(dev, "page request queue length set to %i\n", iommu->priq_len);
>> +
>>          dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
>>