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From:   Florian Eckert <fe@dev.tdt.de>
To:     mturquette@baylibre.com, sboyd@kernel.org, yzhu@maxlinear.com,
        rtanwar@maxlinear.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org
Cc:     linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, Eckert.Florian@googlemail.com
Subject: [PATCH 0/2] clk: mxl: add mxl,control-gate dts property
Date:   Mon, 31 Jul 2023 12:03:47 +0200
Message-ID: <20230731100349.184553-1-fe@dev.tdt.de>
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Gate clocks can be controlled either from this cgu clk driver or directly
from power management driver/daemon. It is dependent on the power
policy/profile requirements of the end product. To take control of gate c=
lks
from this driver.

Until now, the source code had to be changed for this purpose by adding t=
he
flag 'GATE_CLK_HW' to the LGM_GATE macro in the source file
'drivers/clk/x86/clk-lgm.c'.

This can be better handled via the device tree, so that the source no
longer needs to be changed. For this purpose, a new option
'mxl,control-gate' is added, which specifies that the gate is controlled
by this driver.

Florian Eckert (2):
  clk: mxl: add mxl,control-gate dts property
  dt-bindings: clock: intel,cgu-lgm: add mxl,control-gate option

 .../bindings/clock/intel,cgu-lgm.yaml         | 11 +++++++
 drivers/clk/x86/clk-cgu.c                     | 30 +++++++++++--------
 2 files changed, 28 insertions(+), 13 deletions(-)

--=20
2.30.2