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From:   Florian Eckert <fe@dev.tdt.de>
To:     mturquette@baylibre.com, sboyd@kernel.org, yzhu@maxlinear.com,
        rtanwar@maxlinear.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org
Cc:     linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, Eckert.Florian@googlemail.com
Subject: [PATCH 1/2] clk: mxl: add mxl,control-gate dts property
Date:   Mon, 31 Jul 2023 12:03:48 +0200
Message-ID: <20230731100349.184553-2-fe@dev.tdt.de>
In-Reply-To: <20230731100349.184553-1-fe@dev.tdt.de>
References: <20230731100349.184553-1-fe@dev.tdt.de>
MIME-Version: 1.0
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Gate clocks can be controlled either from this cgu clk driver or directly
from power management driver/daemon. It is dependent on the power
policy/profile requirements of the end product. To take control of gate
clks from this driver.

Until now, the source code had to be changed for this purpose by adding
the flag 'GATE_CLK_HW' to the LGM_GATE macro in the source file
'drivers/clk/x86/clk-lgm.c'.

This can be better handled via the device tree, so that the source no
longer needs to be changed. For this purpose, a new option
'mxl,control-gate' is added, which specifies that the gate is controlled
by this driver.

Signed-off-by: Florian Eckert <fe@dev.tdt.de>
---
 drivers/clk/x86/clk-cgu.c | 30 +++++++++++++++++-------------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
index 89b53f280aee..cb4e92ea54bf 100644
--- a/drivers/clk/x86/clk-cgu.c
+++ b/drivers/clk/x86/clk-cgu.c
@@ -339,6 +339,8 @@ int lgm_clk_register_branches(struct lgm_clk_provider=
 *ctx,
 {
 	struct clk_hw *hw;
 	unsigned int idx;
+	const char *name;
+	unsigned int count, i;
=20
 	for (idx =3D 0; idx < nr_clk; idx++, list++) {
 		switch (list->type) {
@@ -355,19 +357,21 @@ int lgm_clk_register_branches(struct lgm_clk_provid=
er *ctx,
 			hw =3D lgm_clk_register_fixed_factor(ctx, list);
 			break;
 		case CLK_TYPE_GATE:
-			if (list->gate_flags & GATE_CLK_HW) {
-				hw =3D lgm_clk_register_gate(ctx, list);
-			} else {
-				/*
-				 * GATE_CLKs can be controlled either from
-				 * CGU clk driver i.e. this driver or directly
-				 * from power management driver/daemon. It is
-				 * dependent on the power policy/profile requirements
-				 * of the end product. To override control of gate
-				 * clks from this driver, provide NULL for this index
-				 * of gate clk provider.
-				 */
-				hw =3D NULL;
+			/* Check if cgu should control the gate clock */
+			hw =3D NULL;
+			count =3D of_property_count_strings(ctx->np,
+							  "mxl,control-gate");
+			if (count <=3D 0)
+				break;
+			for (i =3D 0; i < count; i++) {
+				of_property_read_string_index(ctx->np,
+							      "mxl,control-gate",
+							      i, &name);
+				if (!strncmp(list->name, name, strlen(list->name))) {
+					dev_err(ctx->dev, "enable gate control for %s\n",
+						list->name);
+					hw =3D lgm_clk_register_gate(ctx, list);
+				}
 			}
 			break;
=20
--=20
2.30.2