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bh=3qqk/kt6+Ga7PWsdfCK1cL1LbXt2AwvGMSRMyEpCfxI=; b=OC1cFdOLl0qG1hJyPlTdxK7NBPhhi901H4f6LjrbJ5Db2Yb2XSiHlMNz5QNsMNWAPW x7B+q4zAxSYXueXdRlJ6gdx/6sFB71FCR8YhhFS3fyhlgH0r+kfeqdGXfR2elTK/RglJ QXA7Ms3Fl4lNBqYvVIh1jIX+CZvV88eEYncmzG2r6FQUcEANtgoBo18rugZR+PAwUomr AJ485S5s0IPLqh0X3sCIhqC0l8wous+gQhyBBM7whgWp00xygVj6DTYbVmoc3xmw6Afl EU7v1nRo9qWVOkG+Pd/PSGF/CpyS/gO7ABYyI0TwC/OhXYjydpx5GSW/Ul5bOseqX79Z ODwg== X-Gm-Message-State: ABy/qLZ2ccpquaAp54WxzUxJldHawzCvorizs7mxGue86zkPzoICoClX 7vwPhd7u2g+sE4dbrlmqNJM73K/Rp4K9iXSd0aw= X-Received: by 2002:a05:6602:8b:b0:786:26f0:3092 with SMTP id h11-20020a056602008b00b0078626f03092mr7456305iob.3.1690803934488; Mon, 31 Jul 2023 04:45:34 -0700 (PDT) MIME-Version: 1.0 References: <20230702203429.237615-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20230702203429.237615-4-prabhakar.mahadev-lad.rj@bp.renesas.com> <20230731-tribute-splashing-6a90f443cefe@wendy> In-Reply-To: <20230731-tribute-splashing-6a90f443cefe@wendy> From: "Lad, Prabhakar" Date: Mon, 31 Jul 2023 12:45:08 +0100 Message-ID: Subject: Re: [PATCH v10 3/6] riscv: mm: dma-noncoherent: nonstandard cache operations support To: Conor Dooley Cc: Jisheng Zhang , Arnd Bergmann , Geert Uytterhoeven , Guo Ren , Andrew Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-riscv@lists.infradead.org, Christoph Hellwig , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Conor, On Mon, Jul 31, 2023 at 12:39=E2=80=AFPM Conor Dooley wrote: > > On Mon, Jul 31, 2023 at 12:30:43PM +0100, Lad, Prabhakar wrote: > > On Sun, Jul 30, 2023 at 4:09=E2=80=AFPM Jisheng Zhang wrote: > > > On Sun, Jul 02, 2023 at 09:34:26PM +0100, Prabhakar wrote: > > > > From: Lad Prabhakar > > > > > +config RISCV_NONSTANDARD_CACHE_OPS > > > > + bool > > > > + depends on RISCV_DMA_NONCOHERENT > > > > + help > > > > + This enables function pointer support for non-standard nonc= oherent > > > > + systems to handle cache management. > > > > > > Per Documentation/riscv/patch-acceptance.rst: > > > > > > "we'll only consider patches for extensions that either: > > > > > > - Have been officially frozen or ratified by the RISC-V Foundation, o= r > > > - Have been implemented in hardware that is widely available, per sta= ndard > > > Linux practice." > > > > > > I'm not sure which item this patch series belongs to. > > > > > Maybe Conor can help me here ;) > > I'm not entirely sure why you need my help, it's your company that > manufactures the SoC that needs this after all.. I think Emil already > pointed out that it was the latter of the two. I guess it is not an > "extension" in the strictest sense of the word, but it fills the same > gap as one, so /shrug. > Aaha I was wondering If there had to be an additional entry here to fit this case, but if it already does fit in ignore me. Thanks for the clarification. Cheers, Prabhakar