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Message-ID: <780aa090-3a97-abab-271f-59790df29cc4@linaro.org>
Date:   Mon, 31 Jul 2023 14:03:24 +0200
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Subject: Re: [PATCH 2/2] dt-bindings: clock: intel,cgu-lgm: add
 mxl,control-gate option
To:     Florian Eckert <fe@dev.tdt.de>, mturquette@baylibre.com,
        sboyd@kernel.org, yzhu@maxlinear.com, rtanwar@maxlinear.com,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org
Cc:     linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, Eckert.Florian@googlemail.com
References: <20230731100349.184553-1-fe@dev.tdt.de>
 <20230731100349.184553-3-fe@dev.tdt.de>
Content-Language: en-US
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <20230731100349.184553-3-fe@dev.tdt.de>
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On 31/07/2023 12:03, Florian Eckert wrote:
> Add the new option 'mxl,control-gate'. Gate clocks can be controlled
> either from this cgu clk driver or directly from power management
> driver/daemon. It is dependent on the power policy/profile requirements
> of the end product. To take control of gate clks from this driver, add the
> name of the gate to this <mxl,control-gate> devicetree property.
> Please refer to 'drivers/clk/x86/clk-lgm.c' source file for the gate names.

Choosing which driver controls clocks is OS policy, not DT property. Any
reference to drivers in property description is already a warning sign.

You described the desired Linux feature or behavior, not the actual
hardware. The bindings are about the latter, so instead you need to
rephrase the property and its description to match actual hardware
capabilities/features/configuration etc.


Best regards,
Krzysztof