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From:   Zong Li <zong.li@sifive.com>
Date:   Mon, 31 Jul 2023 21:15:53 +0800
Message-ID: <CANXhq0puxuHA2cEyb2+TobkoFTc=7MQqtv7DYbuZdvf0T8+iUQ@mail.gmail.com>
Subject: Re: [PATCH 06/11] RISC-V: drivers/iommu/riscv: Add command, fault,
 page-req queues
To:     Nick Kossifidis <mick@ics.forth.gr>
Cc:     Tomasz Jeznach <tjeznach@rivosinc.com>,
        Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
        Robin Murphy <robin.murphy@arm.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Anup Patel <apatel@ventanamicro.com>,
        Albert Ou <aou@eecs.berkeley.edu>, linux@rivosinc.com,
        linux-kernel@vger.kernel.org, Sebastien Boeuf <seb@rivosinc.com>,
        iommu@lists.linux.dev, Palmer Dabbelt <palmer@dabbelt.com>,
        linux-riscv@lists.infradead.org
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On Mon, Jul 31, 2023 at 5:32=E2=80=AFPM Nick Kossifidis <mick@ics.forth.gr>=
 wrote:
>
> On 7/29/23 15:58, Zong Li wrote:
> > On Thu, Jul 20, 2023 at 3:34=E2=80=AFAM Tomasz Jeznach <tjeznach@rivosi=
nc.com> wrote:
> >> +       iommu->cap =3D riscv_iommu_readq(iommu, RISCV_IOMMU_REG_CAP);
> >> +
> >> +       /* For now we only support WSIs until we have AIA support */
> >
> > I'm not completely understand AIA support here, because I saw the pci
> > case uses the MSI, and kernel seems to have the AIA implementation.
> > Could you please elaborate it?
> >
>
> When I wrote this we didn't have AIA in the kernel, and without IMSIC we
> can't have MSIs in the hart (we can still have MSIs in the PCIe controlle=
r).

Thanks for your clarification, do we support the MSI in next version?

>
> >
> > Should we define the "interrupt-names" in dt-bindings?
> >
>
> Yes we should, along with queue lengths below.
>
> >> +
> >> +       /* Make sure fctl.WSI is set */
> >> +       fctl =3D riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL);
> >> +       fctl |=3D RISCV_IOMMU_FCTL_WSI;
> >> +       riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FCTL, fctl);
> >> +
> >> +       /* Parse Queue lengts */
> >> +       ret =3D of_property_read_u32(pdev->dev.of_node, "cmdq_len", &i=
ommu->cmdq_len);
> >> +       if (!ret)
> >> +               dev_info(dev, "command queue length set to %i\n", iomm=
u->cmdq_len);
> >> +
> >> +       ret =3D of_property_read_u32(pdev->dev.of_node, "fltq_len", &i=
ommu->fltq_len);
> >> +       if (!ret)
> >> +               dev_info(dev, "fault/event queue length set to %i\n", =
iommu->fltq_len);
> >> +
> >> +       ret =3D of_property_read_u32(pdev->dev.of_node, "priq_len", &i=
ommu->priq_len);
> >> +       if (!ret)
> >> +               dev_info(dev, "page request queue length set to %i\n",=
 iommu->priq_len);
> >> +
> >>          dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
> >>