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From:   Leo Li <leoyang.li@nxp.com>
To:     Andrew Lunn <andrew@lunn.ch>
CC:     Heiner Kallweit <hkallweit1@gmail.com>,
        Russell King <linux@armlinux.org.uk>,
        "David S . Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        David Bauer <mail@david-bauer.net>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Viorel Suman <viorel.suman@nxp.com>,
        Wei Fang <wei.fang@nxp.com>
Subject: RE: [PATCH v3 1/2] net: phy: at803x: fix the wol setting functions
Thread-Topic: [PATCH v3 1/2] net: phy: at803x: fix the wol setting functions
Thread-Index: AQHZwZ33oD8fGtEVxE+PIFQQ7nRsG6/QZg0AgAOSwaA=
Date:   Mon, 31 Jul 2023 14:58:21 +0000
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> -----Original Message-----
> From: Andrew Lunn <andrew@lunn.ch>
> Sent: Saturday, July 29, 2023 3:14 AM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: Heiner Kallweit <hkallweit1@gmail.com>; Russell King
> <linux@armlinux.org.uk>; David S . Miller <davem@davemloft.net>; Jakub
> Kicinski <kuba@kernel.org>; David Bauer <mail@david-bauer.net>;
> netdev@vger.kernel.org; linux-kernel@vger.kernel.org; Viorel Suman
> <viorel.suman@nxp.com>; Wei Fang <wei.fang@nxp.com>
> Subject: Re: [PATCH v3 1/2] net: phy: at803x: fix the wol setting functio=
ns
>=20
> On Fri, Jul 28, 2023 at 04:53:19PM -0500, Li Yang wrote:
> > In commit 7beecaf7d507 ("net: phy: at803x: improve the WOL feature"),
> > it seems not correct to use a wol_en bit in a 1588 Control Register
> > which is only available on AR8031/AR8033(share the same phy_id) to
> > determine if WoL is enabled.  Change it back to use
> > AT803X_INTR_ENABLE_WOL for determining the WoL status which is
> > applicable on all chips supporting wol. Also update the
> > at803x_set_wol() function to only update the 1588 register on chips hav=
ing
> it.
>=20
> Do chips which do not have the 1588 register not have WoL? Or WoL
> hardware is always enabled, but you still need to enable the interrupt.

Some of them do and some don't, which is removed in the other patch from th=
e series.  Since I don't find the register to enable it, I guess it always =
enabled.

>=20
> Have you tested on a range of PHY? It might be better to split this patch=
 up a
> bit. If it causes regressions, having smaller patches can make it easier =
to find
> which change broken it.

No, I only have AR8035 to test with.  Changes for other chips are according=
 to the datasheet.  It would be good if others having the hardware can test=
 it too.

The problem right now on our board with AR8035 is that it gets the wrong Wo=
L setting and fails to enter sleep:
[  354.196156] Qualcomm Atheros AR8035 0x0000000008b96000:02: PM: dpm_run_c=
allback(): mdio_bus_phy_suspend+0x0/0x110 returns -16
[  354.196172] Qualcomm Atheros AR8035 0x0000000008b96000:02: PM: failed to=
 suspend: error -16

Regards,
Leo